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the following document contains information on cypress products. the document has the series name, product name, and ordering part numbering with the prefix mb. however, cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix cy. how to check the ordering p art n umber 1. g o to www.cypress.com/pcn . 2. enter the keyword ( for example , ordering part number) i n the search pcns field and click apply . 3. click the corresponding title from the search results. 4. download the affected parts list file , which has details of all changes for more information please contact your local sales office for additional information about cypress products and solutions. about cypress cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. cypress' microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated products and get them to market first. cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrup t markets by creating new product categories in record time. to learn more, go to www.cypress.com .
mb91580m/s series, fr81s 32- bit microcontroller datasheet cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408- 943- 2600 document number: 002- 0466 5 rev * a revised march 29, 2016 mb91f583amg/amh/amj/amk/asg/ash/asj/ask mb91f584amg/amh/amj/amk/asg/ash/asj/ask mb91f585am g/amh/amj/amk/asg/ash/asj/ask this series is a cypress 32- bit microcontroller for automobile motor control. they use the fr81s cpu that is compatible with the fr family. features fr81s cpu core ? 32- bit risc, load/store architecture, pipeline 5- stage structure ? maximum operating frequen cy: 128mhz (source oscillation= 4.0mhz, 32 multiplied ( pll clock multiplication system) ) ? general - purpose register: 32 bits 16 sets ? 16- bit fixed length instructions (basic instructions), 1 instruction per cycle ? instructions appropriate to embedded applications ? memory -to - memory transfer instructions ? bit manipulation instructions ? barrel shift instructions ? high - level language su pport instructions ? function entry/exit instructions ? register content multi - load and store instructions ? bit search instructions logical 1 detection, 0 detection, and change - point detection ? branch instructions with delay slot overhead decrement during branc h process ? register interlock function easy assembler writing ? built - in multiplier and instruction level support ? signed 32 - bit multiplication: 5 cycles ? signed 16 - bit multiplication: 3 cycles ? interrupt (pc/ps saving) 6 cycles (16 priority levels) ? the harvard architecture allows simultaneous execution of program and data access. ? instruction compatibility with the fr family ? built - in memory protection function (mpu) ? eight protection areas can be specified commonly for instructions and data. ? control access priv ilege in both privilege mode and user mode ? built - in fpu (floating- point operation) ? ieee754 compliant ? floating - point register: 32 bit s 1 6 sets peripheral functions ? clock generation (sscg function is available) ? main oscillation (4 mhz to 20 mhz) ? pll multiplication rate:1 to 32 times ? cr oscillation ? oscillation frequency: 100khz, with frequency accuracy 5 0% (pre - trimming) ? trimming is ena bled ? to be used as a count clock of hardware watchdog ? oscillation stop feature during standby is not available mb91f583 a mj/f584a mj/f585 a mj/f583a mk/f 584a mk/f585amk mb91f583 a sj/f584 a sj/f585 a sj/f583 a sk/f5 84a sk/f585 ask ? oscillation stop feature during standby i s available mb91f583 a mg/f584a mg/f585 a mg/f583a mh /f584 a mh/f585amh mb91f583 a sg/f584 a sg/f585 a sg/f583a sh/ f584 a sh/f585 ash ? built - in program flash memory capacity mb91f583: 256+64 kbytes mb91f584: 384+64 kbytes mb91f585: 512+64 kbytes ? built - in data flash (work f las h) 64 kbytes ? built - in ram capacity ? main ram mb91f583: 32 kbytes mb91f584: 48 kbytes mb91f585: 48 kbytes ? backup ram 8 kbytes ? general - purpose port: mb91f583 a m/f584a m/f585 a m 76 ports including eight i 2 c pseudo open drain corresponding ports mb91f583 as/ f584 a s/f585a s 44ports including two i 2 c pseudo open drain corresponding ports
document number: 002- 0466 5 rev * a page 2 of 175 mb91580m/s series ? dma controller ? up to 8 channels can be started simultaneously. ? 2 transfer factors (internal peripheral request and software) ? external interrupt input mb91f583 a m/f584a m/f585 a m: 8 channels mb91f583 a s/f584a s/f585a s: 7 channels level ("h" / "l") or edge detection (rising or falling) enabled ? multi - function serial communication (built - in transmission/reception fifo memory) mb91f583 a m/f584a m/f585 a m: 4 channels mb91f583 a s/f584a s/f585a s: 2 channels ? uart (asynchronous serial interface) ? full - duplex double buffering system, 64- byte transmission fifo memory, 64 - byte reception fifo memory ? parity or no parity is selectable. ? built - in dedicated baud rate generator ? an external clock can be use d as the transfer clock ? parity, frame, and overrun error detect ion functions provided ? dma transfer supported ? csio (synchronous serial interface) ? full - duplex double buffering system, 64- byte transmission fifo memory, 64 - byte reception fifo memory ? spi suppor ted; master and slave systems supported; 5 to 16, 20, 24, 32 - bit data length can be set. ? built - in dedicated baud rate generator (master operation) ? an external clock can be entered. (slave operation) ? overrun error detect ion function is provided. ? built - in chip selection function ? dma transfer supported ? lin interface (v2.1) ? full - duplex double buffering system, 64- byte transmission fifo memory, 64 - byte reception fifo memory ? lin protocol revision2.1 supported. ? master and slave systems supported ? framing error a nd overrun error detection ? lin sync break generation and detection; lin sync delimiter generation ? built - in dedicated baud rate generator ? an external clock can be adjusted by the reload counter. ? dma transfer supported ? i 2 c ? mb91f583 a m/f584a m/f585 a m: supporte d for 3 channels: ch.0,ch. 2 ,and ch.3 mb91f583 a s/f584a s/f585a s: supported for 1 channel: ch.0 ? full - duplex double buffering system, 64- byte transmission fifo memory, 64 - byte reception fifo memory ? standard mode (max. 100 k bps) / high - speed mode (max. 400 k bps ) supported ? dma transfer supported (for transmission only) ? can controller (can) mb91f583 a m/f584a m/f585 a m: 2 channels mb91f583 a s/f584a s/f585a s: 1 channel ? transfer speed: up to 1mbps ? 64- transmission/reception message buffering ? flexray controller mb91f583 a mg/ f584 a mg/f585 a mg/f583a mj/f584 a mj/f585 a mj/ f583 a sg/f584 a sg/f585 a sg/f583a sj/f584 a sj/f58 5 a sj: 1 unit (ch.a/ch.b) ? flexray specifications version 2.1 supported ? up to 128 message buffers ? 8k bytes of message ram ? variable length of message buffers ? each message buff er can be allocated as a part of reception buffer, transmission buffer or reception fifo memory ? host access to the message buffer via input and output buffers ? filtering for slot counter, cycle counter and channels ? maskable interrupts are supported ? ppg: 16 bits 6 channels ? reload timer: 16 bits 4 channels ? a/d converter (successive approximation type) ? 12- bit resolution mb91f583 a m/f584a m/f585 a m: 3 units (23 channels) mb91f583 a s/f584a s/f585a s: 3 units (17 channels) ? conversion time: 1 s ? free - run timer 16 bi ts 6 channels (1 channel can be selected for input capture, and 1 channel for output compare.) ? input capture: 16 bits 4 channels (linked to the free - run timer) ? output compare: 16 bits 7 channels (linked to the free - run timer) ? waveform generator: 2 un its (7 channels) ? 10- bit d/a converter: 1 channel ? calibration: the hardware watchdog for cr oscillation drive the cr oscillation frequency can be trimmed.
document number: 002- 0466 5 rev * a page 3 of 175 mb91580m/s series ? clock supervisor ? anomaly supervisory feature (by damaged quart z , etc.) of external main oscillation ( 4mhz) ? when anomaly is detected, clock is switched to cr. ? up/ down counter: 2 channels ? 8/16 - bit up/ down counter ? base timer: 2 channels ? 16- bit timer ? any of four pwm/ppg/pwc/reload timer functions can be selected and used. ? as for the functions of pwc and re load timer, 2 channels of cascade mode can be used as 32 - bit timer . ? crc generation ? watchdog timer ? hardware watchdog ? software watchdog ? nmi ? interrupt controller ? interrupt request batch read multiple interrupts from peripherals can be read by a series of reg isters. ? i/o relocation (mb91f583 a m/f584a m/f585am) change of pin position of peripher al functions ? low - power consumption mode ? sleep/stop/watch ? stop (power shut down )/watch (power shut down ) ? power - on reset ? low - voltage detection reset (external low - voltage det ection) ? low - voltage detection reset (internal low - voltage detection) ? package mb91f583 a m/f584a m/f585 a m: lqfp -100 mb91f583 a s/f584a s/f585a s: lqfp -64 ? cmos 90 nm technology ? power supplies ? single 5v power supply ? the voltage s tep - down circuit brings the 5.0v down to generate 1.2v internally ? i/o 5.0v
document number: 002- 0466 5 rev * a page 4 of 175 mb91580m/s series contents 1. product lineup ............................................................................................................................................. 5 2. pin assignment ........................................................................................................................................... 11 3. pin description ........................................................................................................................................... 13 4. i/o circuit type ........................................................................................................................................... 25 5. handling precautions ................................................................................................................................. 31 6. handling devices ........................................................................................................................................ 34 7. block diagram ............................................................................................................................................. 37 8. memory map ................................................................................................................................................ 39 9. i/o map ......................................................................................................................................................... 40 10. interrupt vector table ........................................................................................................................... 117 11. electrical characteristics ..................................................................................................................... 124 11.1 absolute maximum ratings .................................................................................................................... 124 11.2 dc characteristics .................................................................................................................................. 127 11.3 ac characteristics .................................................................................................................................. 134 11.3.1 main clock timing .............................................................................................................................. 134 11.3.2 reset input .......................................................................................................................................... 137 11.3.3 p ower - on conditions .......................................................................................................................... 138 11.3.4 multi - function serial ............................................................................................................................ 139 11.3.5 timer input timing .............................................................................................................................. 157 11.3.6 trigger input timing ............................................................................................................................ 157 11.3.7 nmi input timing ................................................................................................................................. 158 11.3.8 low - voltage detection (external low - vol tage detection) .................................................................... 159 11.3.9 low - voltage detection (internal low - voltage detection) ..................................................................... 159 11.4 a/d converter ......................................................................................................................................... 160 11.4.1 electrical characteristics .................................................................................................................... 160 11.4.2 definition of terms .............................................................................................................................. 161 11.4.3 notes o n using a/d converter ............................................................................................................ 161 11.5 d/a converter ......................................................................................................................................... 163 11.6 flash memory ......................................................................................................................................... 163 11.6.1 electrical characteristics .................................................................................................................... 163 11.6.2 notes .................................................................................................................................................. 164 12. example characteristics ...................................................................................................................... 165 13. ordering information ............................................................................................................................ 169 14. package dimensions ............................................................................................................................ 170 15. major changes ...................................................................................................................................... 172
document number: 002- 0466 5 rev * a page 5 of 175 mb91580m/s series 1. p roduct l ineup mb91580 a m series product lineup comparison ? memory size items mb91f583 a mg mb91f583 a mh mb91f583 a mj mb91f583 a mk mb91f584 a mg mb91f584 a mh mb91f584 a mj mb91f584 a mk mb91f585 a mg mb91f585 a mh mb91f585 a mj mb91f585 a mk flash memory capacit y (program) 256+64 kbytes 384+64 kbytes 512+64 kbytes flash memory capacity (work) 64 kbytes ram capacity (main) 32 kbytes 48 kbytes 48 kbytes ram capacity (backup) 8 kbytes ? function items mb91f583 a mg mb91f584 a mg mb91f585 a mg mb91f583 a mh mb91f584 a mh mb9 1f585 a mh mb91f583 a mj mb91f584 a mj mb91f585 a mj mb91f583 a mk mb91f584 a mk mb91f585 a mk system clock on - chip pll clock multiplication system (up to 32 times of multiplication) minimum instruction execution time: 7.81ns (128mhz, source oscillation 4mhz 32 times of multiplication) cr oscillation provided oscillation stop feature during standby provided provided not provided not provided external bus interface not provided dma transfer 8 channels 16- bit base timer 2 channels free - run timer 6 channels input capture 4 channels output compare 7 channels waveform generator 2 units (7 channels) 16- bit reload timer 4 channels ppg 6 channels external interrupt 8 channels a/d converter 3 units (23 channels) r/d converter not provided d/a converter provided up/ down counter 2 channels multi - function serial interface 4 channels can 64msb 2 channels (ch.0/ch.1) flexray 128msb 1 unit (ch.a / ch.b) not provided 128msb 1 unit (ch.a / ch.b) not provided software watchdog provided hardware watchdog pro vided
document number: 002- 0466 5 rev * a page 6 of 175 mb91580m/s series items mb91f583 a mg mb91f584 a mg mb91f585 a mg mb91f583 a mh mb91f584 a mh mb9 1f585 a mh mb91f583 a mj mb91f584 a mj mb91f585 a mj mb91f583 a mk mb91f584 a mk mb91f585 a mk crc generation 2 channels low - voltage detection reset (internal low - voltage detection) provided low - voltage detection reset (external low - voltage detection) provided device package lqfp - 100 debug interface built - in ocd (on chip debug unit)
document number: 002- 0466 5 rev * a page 7 of 175 mb91580m/s series mb 91580 a s series product lineup comparison ? memory size items mb91f583 a sg mb91f583 a sh mb91f583 a sj mb91f583 a sk mb91f584 a sg mb91f584 a sh mb91f584 a sj mb91f584 a sk mb91f585 a sg mb91f585 a sh mb91f585 a sj mb91f585 a sk flash memory capacity (program) 256+64 kbytes 384+6 4 kbytes 512+64 kbytes flash memory capacity (work) 64 kbytes ram capacity (main) 32 kbytes 48 kbytes 48 kbytes ram capacity (backup) 8 kbytes ? function items mb91f583 a sg mb91f584 a sg mb91f585 a sg mb91f583 a sh mb91f584 a sh mb91f585 a sh mb91f583 a sj mb91f584 a sj mb91f585 a sj mb91f583 a sk mb91f584 a sk mb91f585 a sk system clock on - chip pll clock multiplication system (up to 32 times of multiplication) minimum instruction execution time: 7.81ns (128mhz, source oscillation 4mhz 32 times of multiplication) cr oscillation provided oscillation stop feature during standby provided provided not provided not provided external bus interface not provided dma transfer 8 channels 16- bit base timer 2 channels free - run timer 6 chan nels input capture 4 channels output compare 7 channels waveform generator 2 units (7 channels) 16- bit reload timer 4 channels ppg 6 channels external interrupt 7 channels a/d converter 3 units (17 channels) r/d converter not provided d/a converte r provided up/ down counter 2 channels multi - function serial interface 2 channels can 64msb 1 channel (ch.0) flexray 128msb 1unit (ch.a / ch.b) not provided 128msb 1unit (ch.a / ch.b) not provided software watchdog provided hardware watchdog provided crc generation 2 channels
document number: 002- 0466 5 rev * a page 8 of 175 mb91580m/s series items mb91f583 a sg mb91f584 a sg mb91f585 a sg mb91f583 a sh mb91f584 a sh mb91f585 a sh mb91f583 a sj mb91f584 a sj mb91f585 a sj mb91f583 a sk mb91f584 a sk mb91f585 a sk low - voltage detection reset (internal low - voltage detection) provided low - voltage detection reset (external low - voltage detection) provided device package lqfp - 64 debug interface built - in ocd (on chip debug unit)
document number: 002- 0466 5 rev * a page 9 of 175 mb91580m/s series mb91580l series product lineup comparison ? memory size items mb91f585la mb91f585lb mb91f585lc mb9 1f585ld mb91f586la mb91f586lb mb91f586lc mb91f586ld mb91f587la mb91f587lb mb91f587lc mb91f587ld flash memory capacity (program) 512+64 kbytes 768+64 kbytes 1024+64 kbytes flash memory capacity (work) 64 kbytes ram capacity (main) 48 kbytes 64 kbytes 96 kbytes ram capacity (backup) 8 kbytes ? function items mb91f585la mb91f586la mb91f587la mb91f585lb mb91f586lb mb91f587lb mb91f585lc mb91f586lc mb91f587lc mb91f585ld mb91f586ld mb91f587ld system clock on - chip pll clock multiplication system (up to 32 time s of multiplication) minimum instruction execution time: 7.81ns (128mhz, source oscillation 4mhz 32 times of multiplication) cr oscillation provided oscillation stop feature during standby provided provided not provided not provided external bus interface not provided address: 22 bits data: 16 bits not provided address: 22 bits data: 16 bits dm a transfer 8 channels 16- bit base timer 2 channels free - run timer 6 channels input capture 8 channels output compare 12 channels waveform generator 2 units (12 channels) 16- bit reload timer 4 channels ppg 24 channels external interrupt 8 channels a/d converter 3 units (24 channels) r/d converter provided not provided provided not provided d/a converter not provided provided not provided provided up/ down counter 2 channels multi - function serial interface 5 channels can 64 msb 3 channels (ch.0/ch.1/ch.2) flexray 128 msb 1 unit (ch.a / ch.b) software watchdog provided hardware watchdog provided crc generation 1 channel
document number: 002- 0466 5 rev * a page 10 of 175 mb91580m/s series items mb91f585la mb91f586la mb91f587la mb91f585lb mb91f586lb mb91f587lb mb91f585lc mb91f586lc mb91f587lc mb91f585ld mb91f586ld mb91f587ld low - voltage detection reset (internal low - voltage detection) provided low - voltage detection reset (ext ernal low - voltage detection) provided device package lqfp - 144 debug interface built - in ocd (on chip debug unit) note : for details on the mb91580l series, see the "mb91580l series hardware manual".
document number: 002- 0466 5 rev * a page 11 of 175 mb91580m/s series 2. p in a ssignment lqfp -100 pin assignment mb91f583am/f58 4am/f585am (top view) v cc 5 p 070 / t i n 0 /i n t3 p 047 / t o t0 / i n t 2 / a d t g 2 p 046 / a d t g 0 / m m p 08 7 p 08 6 p 085 / s c s 3 c vs s p 084 / s c k 3 p 083 / s o t 3 p 082 / s i n 3 rs t x p 045 / r x 0 / i n t 1 p 044 / t x 0 vs s x 1 x 0 p 081 / s c k 0_ 1 p 080 / s o t 0 _ 1 p 043 / s i n 0_1 / a d t g 1 / m o n c l k debu g i f vcc 5 10 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 v s s 1 p 071 / t i n 1 / a i n 0 / i n t 4 3 p 00 1 4 p 072 / t o t1 / b i n 0 / r t o 6 5 p 050 / r t o 5 / z i n 0 6 p 00 2 7 p 051 / r t o 4 / a i n 1 / f rc k 5 8 p 00 3 9 p 0 5 2 / r t o 3 / b i n 1 / f rck 4 1 0 6 9 p 0 64 / s c k 2 p 0 0 4 1 1 6 8 p 0 37 / a n 8 p 053 / r t o 2 / z i n 1 / f rc k 3 1 2 6 7 n m i x p 0 0 5 1 3 6 6 p 0 63 / s o t 2 p 054 / r t o 1 / f r c k 2 1 4 6 5 p 06 2 / s i n 2 6 4 p 036 / a n 9 / t i o a 0 / t i n 2 6 3 p 0 35 / a n 10 / t i o b 0 / t o t 2 p 0 0 6 1 5 7 5 v s s p 055 / r t o 0 / f rc k 1 1 6 p 0 0 7 1 7 6 2 p 0 34 / a n 1 1 / t i o a 1 / t i n 3 v c c 5 2 5 6 1 p 0 33 / a n 1 2 / t i o b 1 / t o t 3 6 0 p 061 / t x 1 p 0 1 1 / a n 1 / i n 1 2 0 p 0 1 0 / a n 0 / i n 0 1 9 p 056 / d tt i 0 / f rc k 0 1 8 5 9 p 060 / r x 1 /i n t 7 p 0 1 2 / a n 2 / i n 2 2 1 p 013 / a n 3 / i n 3 2 2 p 0 14 / a n 4 / t r g 1 2 3 p 015 / a n 5 2 4 5 5 p 032 / a n 1 3 5 4 p 031 / a n 1 4 5 3 p 030 / d a o u t 5 2 p 097 / a n 2 3 5 8 a v cc 1 5 7 a v r h 1 5 6 avss 1 / a v r l 1 5 1 vs s 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p 016 / a n 6 / i n t 6 avcc 0 p 017 / a n 7 / i n t 5 avrh 0 avss 0 / av r l 0 p 090 / a n 1 6 vs s p 091 / a n 1 7 p 0 92 / a n 1 8 p 0 20 / sck 1 / t r g 0 p 0 21 / s i n 1 / t xe n b / i n t 0 p 0 22 / s o t 1 / r x d b p 0 23 / s c s 1 / t xd b p 0 24 / pp g 0 / s t o p w t p 0 25 / pp g 1 / t xe n a p 0 26 / pp g 2 / r x d a p 027 / pp g 3 / t x d a p 093 / a n 19 / p p g 4 p 0 94 / a n 20 / pp g 5 p 0 95 / a n 2 1 p 0 96 / a n 2 2 p 1 0 0 p 1 0 1 p 1 0 2 vcc 5 lqf p - 1 0 0 m d 1 m d 0 7 2 p 0 41 / s c k 0_ 0 7 1 p 0 40 / s o t 0_ 0 7 0 p 065 / s c s 2 7 4 p 0 42 / s i n 0_ 0 7 3 p 0 6 6 p 00 0 2 (fp t -100p-m20)
document number: 002- 0466 5 rev * a page 12 of 175 mb91580m/s series lqfp -64 pin assignment mb91f583as/f584as/f585as (top view) v cc 5 p 0 7 0 / t i n 0 /i n t 3 p 0 4 7 / t o t 0 /i n t 2 / a d t g 2 p 04 6 / a d t g 0 / m m c vs s r s t x p 04 5 / r x 0 /i n t 1 p 0 4 4 / t x 0 vs s x 1 x 0 m d 1 m d 0 p 04 3 / a d t g 1 / m onc l k d eb u g i f 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 v s s 1 p 0 72 / t o t 1 / b i n 0 / r t o 6 3 p 05 0 / r t o 5 / z i n 0 4 p 0 5 1 / r t o 4 / a i n 1 / f r c k 5 5 p 0 5 2 / r t o 3 / b i n 1 / f rc k 4 6 p 05 3 / r t o 2 / z i n 1 / f r c k 3 7 p 05 4 / r t o 1 / f rc k 2 8 p 0 5 5 / r t o 0 / f rc k 1 9 p 0 5 6 / d t t i 0 / f r c k 0 1 0 4 2 p 0 35 / a n 1 0 / t i o b 0 / t o t 2 p 0 1 0 / a n 0 /i n 0 1 1 4 1 p 0 34 / a n 1 1 / t io a 1 / t i n 3 p 0 1 1 / a n 1 /i n 1 1 2 4 0 p 0 33 / a n 1 2 / t i o b 1 / t o t 3 p 0 1 2 / a n 2 /i n 2 1 3 p 0 1 3 / a n 3 /i n 3 1 4 3 6 p 0 32 / a n 1 3 p 01 4 / a n 4 / t r g 1 1 5 3 8 a v r h 1 3 7 a vss 1 / a v r l 1 3 3 v s s 3 9 a v c c 1 p 0 1 5 / a n 5 1 6 3 5 p 0 31 / a n 1 4 3 4 p 0 30 / d a o u t 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 av cc 0 p 0 1 7 / a n 7 /i n t 5 av rh 0 avss 0 / av r l 0 p 0 2 0 / s c k 1 / t r g 0 p 0 2 1 / s i n 1 / t x e n b /i n t 0 p 0 1 6 / a n 6 /i n t 6 p 0 2 2 / s o t 1 / r x d b p 0 2 3 / s c s 1 / t x d b p 02 4 / pp g 0 / s t o p w t p 02 5 / pp g 1 / txen a p 0 2 6 / pp g 2 / r x d a p 0 2 7 / pp g 3 / t x d a p 09 3 / a n 1 9 / pp g 4 p 0 9 4 / a n 2 0 / pp g 5 vcc 5 l q f p- 6 4 4 5 p 0 3 7 / a n 8 4 4 n m i x 4 3 p 0 36 / a n 9 / t i o a 0 / t i n 2 4 7 p 0 4 1 / s c k 0 _ 0 4 8 p 0 4 2 / s i n 0 _ 0 4 6 p 0 4 0 / s o t 0 _ 0 p 07 1 / t i n 1 / a i n 0 /i n t 4 2 (fp t -64p-m24)
document number: 002- 0466 5 rev * a page 13 of 1 75 mb91580m/s series 3. p in d escription mb91f583 a m/f584a m/f585 a m pin no. pin name i/o circuit type* function 83 x0 a main clock oscillation input pin 84 x1 main clock oscillation output pin 67 nmix b interrupt input pin without mask 88 rstx b external reset input pin 81 md0 c mode pin 0 (with high - voltage control) 82 md1 c mode pin 1 (with high - voltage control) 2 p000 d general - purpose i/o port 4 p001 d general - purpose i/o p ort 7 p002 d general - purpose i/o port 9 p003 d general - purpose i/o port 11 p004 d general - purpose i/o port 13 p005 d general - purpose i/o port 15 p006 d general - purpose i/o port 17 p007 d general - purpose i/o port 19 p010 f general - purpose i/o port in0 16- bit input capture ch.0 external pulse input pin an0 adc analog 0 input pin 20 p011 f general - purpose i/o port in1 16- bit input capture ch.1 external pulse input pin an1 adc analog 1 input pin 21 p012 f general - purpose i/o port in2 16- bit input capture ch.2 external pulse input pin an2 adc analog 2 input pin 22 p013 f general - purpose i/o port in3 16- bit input capture ch.3 external pulse input pin an3 adc analog 3 input pin 23 p014 f general - purpose i/o port trg1 ppg ch.4, ch.5 external trigger an4 adc analog 4 input pin 24 p015 f general - purpose i/o port an5 adc analog 5 input pin 27 p016 g general - purpose i/o port an6 adc analog 6 input pin int6 int6 external interrupt input pin
document number: 002- 0466 5 rev * a page 14 of 175 mb91580m/s series pin no. pin name i/o circui t type* function 29 p017 g general - purpose i/o port an7 adc analog 7 input pin int5 int5 external interrupt input pin 35 p020 d general - purpose i/o port sck1 multi - function serial ch.1 clock i/o pin trg0 ppg ch.0 to ch.3 external trigger 3 6 p021 l general - purpose i/o port sin1 multi - function serial ch.1 serial data input pin txenb flexray ch.b operation enable output pin int0 int0 external interrupt input pin 37 p022 k general - purpose i/o port sot1 multi - function serial ch.1 s erial data output pin rxdb flexray ch.b data input pin 38 p023 k general - purpose i/o port scs1 multi - function serial ch.1 serial chip select i/o pin txdb flexray ch. a operation enable output pin 39 p024 d general - purpose i/o port ppg0 ppg ch. 0 output pin stopwt flexray stopwatch input pin 40 p025 k general - purpose i/o port ppg1 ppg ch.1 output pin txena flexray ch.a operation enable output pin 41 p026 k general - purpose i/o port ppg2 ppg ch.2 output pin rxda flexray ch.a data i nput pin 42 p027 k general - purpose i/o port ppg3 ppg ch.3 output pin txda flexray ch.a data output pin 53 p030 m general - purpose i/o port daout dac analog output pin 54 p031 f general - purpose i/o port an14 adc analog 14 input pin
document number: 002- 0466 5 rev * a page 15 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 55 p032 f general - purpose i/o port an13 adc analog 13 input pin 61 p033 f general - purpose i/o port tiob1 base timer ch.1 tiob input pin tot3 reload timer ch.3 output pin an12 adc analog 12 input pin 62 p03 4 f general - purpose i/o port tioa1 base timer ch.1 tioa i/o pin tin3 reload timer ch.3 event input pin an11 adc analog 11 input pin 63 p035 f general - purpose i/o port tiob0 base timer ch.0 tiob input pin tot2 reload timer ch.2 output pin an10 adc analog 10 input pin 64 p036 f general - purpose i/o port tioa0 base timer ch.0 tioa output pin tin2 reload timer ch.2 event input pin an9 adc analog 9 input pin 68 p037 f general - purpose i/o port an8 adc analog 8 input pin 71 p040 h general - purpose i/o port sot0_0 multi - function serial ch.0 serial data output pin (0)/ i 2 c ch.0 serial data i/o pin (sda) 72 p041 h general - purpose i/o port sck0_0 multi - function serial ch.0 clock i/o pin (0)/ i 2 c ch.0 clock i/o pin (scl) 74 p042 d general - purpose i/o port sin0_0 multi - function serial ch.0 serial data input pin (0) 78 p043 d general - purpose i/o port sin0_1 multi - function serial ch.0 serial data input pin (1) adtg1 a/d converter ch.8 to ch.14 external trigger input pin mo nclk clock monitor output pin 86 p044 d general - purpose i/o port tx0 can transmission data 0 output pin
document number: 002- 0466 5 rev * a page 16 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 87 p045 e general - purpose i/o port rx0 can reception data 0 input pin int1 int1 external inte rrupt input pin 97 p046 d general - purpose i/o port adtg0 a/d converter ch.0 to ch.7 external trigger input pin mm clock supervisor main clock stop detection output pin 98 p047 e general - purpose i/o port tot0 reload timer ch.0 output pin int2 int2 external interrupt input pin adtg2 a/d converter ch.16 - ch.23 external trigger input pin 6 p050 d general - purpose i/o port rto5 waveform generator ch.5 output pin zin0 up/down counter ch.0 zin input pin 8 p051 d general - purpose i/o port rt o4 waveform generator ch.4 output pin ain1 up/down counter ch.1 ain input pin frck5 free - run timer ch.5 external clock input pin 10 p052 d general - purpose i/o port rto3 waveform generator ch.3 output pin bin1 up/down counter ch.1 bin input pi n frck4 free - run timer ch.4 external clock input pin 12 p053 d general - purpose i/o port rto2 waveform generator ch.2 output pin zin1 up/down counter ch.1 zin input pin frck3 free - run timer ch.3 external clock input pin 14 p054 d general - purpo se i/o port rto1 waveform generator ch.1 output pin frck2 free - run timer ch.2 external clock input pin 16 p055 d general - purpose i/o port rto0 waveform generator ch.0 output pin frck1 free - run timer ch.1 external clock input pin 18 p056 d gen eral - purpose i/o port dtti0 waveform generator output stop signal input pin 0 frck0 free - run timer ch.0 external clock input pin 59 p060 e general - purpose i/o port rx1 can reception data 1 input pin int7 int7 external interrupt input pin
document number: 002- 0466 5 rev * a page 17 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 60 p 061 d general - purpose i/o port tx1 can transmission data 1 output pin 65 p062 d general - purpose i/o port sin2 multi - function serial ch.2 serial data input pin 66 p063 h general - purpose i/o port sot2 multi - function serial ch.2 serial data output pin/ i 2 c ch.2 serial data i/o pin (sda) 69 p064 h general - purpose i/o port sck2 multi - function serial ch.2 clock i/o pin/ i 2 c ch.2 clock i/o pin (scl) 70 p065 d general - purpose i/o port scs2 multi - function serial ch . 2 serial chip select i/o pin 73 p066 d general - purpose i/o port 99 p070 e general - purpose i/o port tin0 reload timer ch.0 event input pin int3 int3 external interrupt input pin 3 p071 e general - purpose i/o port tin1 reload timer ch.1 event input pin ain0 up/down counter ch .0 ain input pin int4 int4 external interrupt input pin 5 p072 d general - purpose i/o port tot1 reload timer ch.1 output pin bin0 up/down counter ch.0 bin input pin rto6 waveform generator ch.6 output pin 79 p080 h general - purpose i/o port s ot0_1 multi - function serial ch.0 serial data output pin (1)/ i 2 c ch.0 serial data i/o pin (1) (sda) 80 p081 h general - purpose i/o port sck0_1 multi - function serial ch.0 clock i/o pin (1)/ i 2 c ch.0 clock i/o pin (1) (scl) 89 p082 d general - purpose i/o port sin3 multi - function serial ch.3 serial data input pin 90 p083 h general - purpose i/o port sot3 multi - function serial ch.3 serial data output pin/ i 2 c ch.3 serial data i/o pin (sda) 91 p084 h general - purpose i/o port sck3 multi - function seri al ch.3 clock i/o pin/ i 2 c ch.3 clock i/o pin (scl)
document number: 002- 0466 5 rev * a page 18 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 94 p085 d general - purpose i/o port scs3 multi - function serial ch.3 serial chip select i/o pin 95 p086 d general - purpose i/o port 96 p087 d general - purpose i/o port 32 p090 f general - purpose i/o po rt an16 adc analog 16 input pin 33 p091 f general - purpose i/o port an17 adc analog 17 input pin 34 p092 f general - purpose i/o port an18 adc analog 18 input pin 43 p093 f general - purpose i/o port ppg4 ppg ch.4 output pin an19 adc analog 19 input pin 44 p094 f general - purpose i/o port ppg5 ppg ch.5 output pin an20 adc analog 20 input pin 45 p095 f general - purpose i/o port an21 adc analog 21 input pin 46 p096 f general - purpose i/o port an22 adc analog 22 input pin 52 p097 f ge neral - purpose i/o port an23 adc analog 23 input pin 47 p100 d general - purpose i/o port 48 p101 d general - purpose i/o port 49 p102 d general - purpose i/o port 77 debugif i debug i/f pin 28 avcc0 - a/d converter analog power supply 58 avcc1 - a/d con verter analog power supply 30 avrh0 - a/d converter upper limit reference voltage 57 avrh1 - a/d converter upper limit reference voltage 31 avss0 - a/d converter gnd avrl0 a/d converter lower limit reference voltage 56 avss1 - a/d converter gnd av rl1 a/d converter lower limit reference voltage 93 c - external capacity connection output pin 25, 50, 76, 100 vcc5 - +5.0 v power supply
document number: 002- 0466 5 rev * a page 19 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 1, 26, 51, 75, 85, 92 vss - gnd * for i/o circuit type s , see 4 i/o circuit type
document number: 002- 0466 5 rev * a page 20 of 175 mb91580m/s series mb91f583 a s/f584a s/f585a s pin no. pin name i/o circuit type* function 53 x0 a main clock oscillation input pin 54 x1 main clock oscillation output pin 44 nmix b interrupt input pin without mask 58 rstx b external reset input pin 51 md0 c mode pin 0 (with high - voltage control) 52 md1 c mode pin 1 (with high - voltage control) 11 p010 f general - purpose i/o port in0 16- bit input capture ch.0 external pulse input pin an0 adc analog 0 input pin 12 p011 f general - purpose i/o port in1 16- bit input capture ch.1 external pulse input pin an1 adc analog 1 input pin 13 p012 f general - purpose i/o port in2 16- bit input capture ch.2 external pulse input pin an2 adc analog 2 input pin 14 p013 f general - purpose i/o port in3 16- bit input capture ch.3 external pulse input pin an3 adc analog 3 input pin 15 p014 f general - purpose i/o port trg1 ppg ch.4, ch.5 external trigger an4 adc analog 4 input pin 16 p015 f general - purpose i/o port an5 adc analog 5 input pin 17 p016 g general - purpose i/o port an6 adc analog 6 input pin int6 int6 external interrupt input pin 19 p017 g general - purpose i/o port an7 adc analog 7 input pin int5 int5 external interrupt input pin 22 p020 d general - purpose i/o port sck1 multi - function serial ch.1 clock i/o pin trg0 ppg ch.0 to ch.3 external trigger 23 p021 l general - purpose i/o port sin1 multi - function serial ch.1 serial data input pin txenb flexray ch.b operation enable output pin int0 int0 external interru pt input pin
document number: 002- 0466 5 rev * a page 21 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 24 p022 k general - purpose i/o port sot1 multi - function serial ch.1 serial data output pin rxdb flexray ch.b data input pin 25 p023 k general - purpose i/o port scs1 multi - function serial ch.1 serial chip select i/o pin txdb flexray ch.b data output pin 26 p024 d general - purpose i/o port ppg0 ppg ch.0 output pin stopwt flexray stopwatch input pin 27 p025 k general - purpose i/o port ppg1 ppg ch.1 output pin txena flexray ch.a operation enable output pin 28 p026 k general - purpose i/o port ppg2 ppg ch.2 output pin rxda flexray ch.a data input pin 29 p027 k general - purpose i/o port ppg3 ppg ch.3 output pin txda flexray ch.a data output pin 34 p030 m general - purpose i/o port daout dac analog output pin 35 p031 f general - purpose i/o port an14 adc analog 14 input pin 36 p032 f general - purpose i/o port an13 adc analog 13 input pin 40 p033 f general - purpose i/o port tiob1 base timer ch.1 tiob input pin t ot3 reload timer ch.3 output pin an12 adc analog 12 input pin 41 p034 f general - purpose i/o port tioa1 base timer ch.1 tioa i/o pin tin3 reload timer ch.3 event input pin an11 adc analog 11 input pin 42 p035 f general - purpose i/o port tiob 0 base timer ch.0 tiob input pin tot2 reload timer ch.2 output pin an10 adc analog 10 input pin
document number: 002- 0466 5 rev * a page 22 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 43 p036 f general - purpose i/o port tioa0 base timer ch.0 tioa output pin tin2 reload timer ch.2 eve nt input pin an9 adc analog 9 input pin 45 p037 f general - purpose i/o port an8 adc analog 8 input pin 46 p040 h general - purpose i/o port sot0_0 multi - function serial ch.0 serial data output pin(0)/ i 2 c ch.0 serial data i/o pin (0) (sda) 47 p041 h general - purpose i/o port sck0_0 multi - function serial ch.0 clock i/o pin (0)/ i 2 c ch.0 clock i/o pin (0) (scl) 48 p042 d general - purpose i/o port sin0_0 multi - function serial ch.0 serial data input pin (0) 50 p043 d general - purpose i/o port ad tg1 a/d converter ch.8 to ch.14 external trigger input pin monclk clock monitor output pin 56 p044 d general - purpose i/o port tx0 can transmission data 0 output pin 57 p045 e general - purpose i/o port rx0 can reception data 0 input pin int1 i nt1 external interrupt input pin 61 p046 d general - purpose i/o port adtg0 a/d converter ch.0 to ch.7 external trigger input pin mm clock supervisor main clock stop detection output pin 62 p047 e general - purpose i/o port tot0 reload timer ch.0 ou tput pin int2 int2 external interrupt input pin adtg2 a/d converter ch.19 to ch.20 external trigger input pin 4 p050 d general - purpose i/o port rto5 waveform generator ch.5 output pin zin0 up/down counter ch.0 zin input pin 5 p051 d general - p urpose i/o port rto4 waveform generator ch.4 output pin ain1 up/down counter ch.1 ain input pin frck5 free - run timer ch.5 external clock input pin
document number: 002- 0466 5 rev * a page 23 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 6 p052 d general - purpose i/o port rto3 waveform g enerator ch.3 output pin bin1 up/down counter ch.1 bin input pin frck4 free - run timer ch.4 external clock input pin 7 p053 d general - purpose i/o port rto2 waveform generator ch.2 output pin zin1 up/down counter ch.1 zin input pin frck3 free - run timer ch.3 external clock input pin 8 p054 d general - purpose i/o port rto1 waveform generator ch.1 output pin frck2 free - run timer ch.2 external clock input pin 9 p055 d general - purpose i/o port rto0 waveform generator ch.0 output pin frc k1 free - run timer ch.1 external clock input pin 10 p056 d general - purpose i/o port dtti0 waveform generator output stop signal input pin 0 frck0 free - run timer ch.0 external clock input pin 63 p070 e general - purpose i/o port tin0 reload timer c h.0 event input pin int3 int3 external interrupt input pin 2 p071 e general - purpose i/o port tin1 reload timer ch.1 event input pin ain0 up/down counter ch.0 ain input pin int4 int4 external interrupt input pin 3 p072 d general - purpose i/o po rt tot1 reload timer ch.1 output pin bin0 up/down counter ch.0 bin input pin rto6 waveform generator ch.6 output pin 30 p093 f general - purpose i/o port ppg4 ppg ch.4 output pin an19 adc analog 19 input pin 31 p094 f general - purpose i/o por t ppg5 ppg ch.5 output pin an20 adc analog 20 input pin 49 debugif i debug i/f pin 18 avcc0 - a/d converter analog power supply 39 avcc1 - a/d converter analog power supply
document number: 002- 0466 5 rev * a page 24 of 175 mb91580m/s series pin no. pin name i/o circuit type* function 20 avrh0 - a/d converter upp er limit reference voltage 38 avrh1 - a/d converter upper limit reference voltage 21 avss0 - a/d converter gnd avrl0 a/d converter lower limit reference voltage 37 avss1 - a/d converter gnd avrl1 a/d converter lower limit reference voltage 60 c - external capacity connection output pin 32, 64 vcc5 - +5.0 v power supply 1, 33, 55, 59 vss - gnd * for i/o circuit type s , see 4 i/o circuit type
document number: 002- 0466 5 rev * a page 25 of 175 mb91580m/s series 4. i/o circuit type type circuit remarks a clock input x0 standby control signal x1 oscil lation feedback resistor: approx. 1 m ? b pull-up resistor cmos hysteresis input ? cmos hysteresis input ? with 50 k ? pull - up resistor c n-ch mode input high withstand voltage mode input high withstand voltage control n-ch n-ch n-ch ? schmitt input ? with high withstand voltage control
document number: 002- 0466 5 rev * a page 26 of 175 mb91580m/s series type circuit remarks d pull-up control digital output cmos hysteresis input automotive input standby control p-ch p-ch n-ch r ? general - purpose i/o port ? cmos level output i oh = -2/ - 5ma, i ol =2/5ma ? with 50k ? pull - up resistor con trol ? cmos hysteresis input (0.7vcc/0.3vcc) ? automotive input (0.8vcc/0.5vcc) e pull-up control digital output cmos hysteresis input automotive input standby control p-ch p-ch n-ch r ? general - purpose i/o port ? cmos level output i oh = -2/ - 5ma, i ol =2/5ma ? with 50 k ? pull - up resistor control ? cmos hysteresis input (0.7vcc/0.3vcc) during standby, the input value r etains the previous value. ? automotive input (0.8vcc/0.5vcc) during standby, the input value retains the previous value.
document number: 002- 0466 5 rev * a page 27 of 175 mb91580m/s series type circuit remarks f pull-up control digital output cmos hysteresis input automotive input standby control analog input p-ch p-ch n-ch r ? with analog input, general - purpose i/o port ? cmos level output i oh = -2/ - 5ma, i ol =2/5ma ? with 50 k ? pull - up resistor control ? cmos h ysteresis input (0.7vcc/0.3vcc) ? automotive input (0.8vcc/0.5vcc) g pull-up control digital output cmos hysteresis input automotive input standby control analog input p-ch p-ch n-ch r ? with analog input, general - purpose i/o port ? cmos level output i oh = -2/ - 5ma, i ol =2/5ma ? with 50 k ? pull - up resistor control ? cmos hysteresis input (0.7vcc/0.3vcc) during standby, the input value retains the previous value. ? automotive input (0.8vcc/0.5vcc) during standby, the input value retains the previous value.
document number: 002- 0466 5 rev * a page 28 of 175 mb91580m/s series type circuit remarks h pull-up control digital output cmos hysteresis input automotive input standby control p-ch p-ch n-ch r ? with i 2 c, general - purpose i/o port ? cmos level output i oh = - 3ma, i ol =3ma (at i 2 c output) i oh = -2/ - 5ma, i ol =2/5ma (other th an above) ? with 50 k ? pull - up resistor control ? cmos hysteresis input (0.7vcc/0.3vcc) ? automotive input (0.8vcc/0.5vcc) i tt l schmitt input digital output open drain i/o
document number: 002- 0466 5 rev * a page 29 of 175 mb91580m/s series type circuit remarks k pull-up control digital output flexray input automotive input standby control p-ch p-ch n-ch r analog output ? with analog output, general - purpose i/o port ? cmos level output i oh = -2/ - 4ma, i ol =2/4ma ? with 50 k ? pull - up resistor control ? flexray input (0. 7 vcc/0.3vcc) ? automotive input (0.8vcc/0.5vccc) l pull-up control digital output flexray input automotive input standby control p-ch p-ch n-ch r analog output ? with analog output, general - purpose i/o port ? cmos level output i oh = -2/ - 4ma, i ol =2/4ma ? with 50 k ? pull - up resistor control ? flexray input (0. 7 vcc/0.3vcc) during standby, the input value retains the previous value. ? automotive input (0.8vcc/0.5vcc) during standby, the input value retains the previous value.
document number: 002- 0466 5 rev * a page 30 of 175 mb91580m/s series type circuit remarks m pull-up control digital output cmos hysteresis input automotive input standby control p-ch p-ch n-ch r d/ a converter output ? with d/a converter output, general - purpose i/o port ? cmos level output i oh = -2/ - 5ma, i ol =2/5ma ? with 50 k ? pull - up resistor control ? cmos hysteresis input (0.7vcc/0.3vcc) ? automotive input (0.8vcc/0.5vcc)
document number: 002- 0466 5 rev * a page 31 of 175 mb91580m/s series 5. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 5.1 precautions for product design this section desc ribes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established lim its, called absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when op erated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operatin g conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause det erioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pi ns, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very h igh impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch -up semiconductor devices are constructed by the formation of p - type and n - type area s on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this con dition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products.
document number: 002- 0466 5 rev * a page 32 of 175 mb91580m/s series ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection , and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, i ndustrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult wit h sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 5.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either cas e, for heat resistance during soldering, you should only mount under cypress 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto pri nted circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave sol dering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mountin g conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting c onditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. ? lead- free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn- pb eutectic soldering, j unction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, th e application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to cond ense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package tha t recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for sto rage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust.
document number: 002- 0466 5 rev * a page 33 of 175 mb91580m/s series ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125c /24 h ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an appar atus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through h igh resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other high ly static - prone materials for storage of completed board assemblies. 5.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactio ns that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to r adiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of th e release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002- 0466 5 rev * a page 34 of 175 mb91580m/s series 6. handling devices the latch - up prevention and pin processing are explained below. ? for latch - up prevention if a voltage higher than vcc or a voltage lower than vss is applied to an i/o pin, or if a voltage exceeding the ratings is applied between vcc and vss pins, a latch - up may occur in cmos ic. if the latch - up occurs, the power supply current incre ases excessively and device elements may be damaged by heat. take care to prevent any voltage from exceeding the maximum ratings in device application. also, the analog power supplies (avcc0, avcc1, avrh0, avrh1) and analog input must not exceed the digita l power supply (vcc5) when the power supply to the analog system is turned on or off. in the correct power - on sequence, turn on the digital power supply voltage (vcc5) and analog power supply voltages (avcc0, avcc1, avrh0, avrh1) simultaneously. alternativ ely, turn on the digital power supply voltage (vcc5) first, and then turn on the analog power supplies (avcc0, avcc1, avrh0, avrh1). ? treatment of unused pins if unused input pins are left open, they may cause a permanent damage to the device due to device malfunction or latch - up. connect a 2k or higher resistor to each of unused input pins for pull - up or pull - down processing. also, if i/o pins are not used, they must be set to the output state for releasing or they must be set to the input state and treat ed in the same way as for the input pins. ? power supply pins the device is designed to ensure that if the device contains multiple vcc or vss pins, the pins that should be at the same potential are interconnected to prevent latch - up or other malfunctions. further, connect these pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. as shown in following figure, all v ss power supply pins must be treated in the similar way. if multiple vcc or vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. ? power supply input pins v cc v cc v cc v cc v ss v ss v ss v ss v ss v cc
document number: 002- 0466 5 rev * a page 35 of 175 mb91580m/s series the power supply pins should be connecte d to vcc and vss of this device at the low impedance from the power supply source. in the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of c pin is recommended to use as a bypass capacitor between vcc and vss pins. ? crystal oscillation circuit an external noise to the x0 or x1 pin may cause a device malfunction. the printed circuit board must be designed to lay out x0 and x1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be gro unded to the close position to the device. the printed circuit board artwork is recommended to surround the x0 and x1 pins by ground circuits. ? mode pin (md[1:0]) connect the md[1:0] mode pin to the vcc or vss pin directly. to prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and vcc or vss pin on the printed circuit board. also, use the low - impedance pin connection. ? during power -on to prevent a malfunction of the voltage step - down circuit built in the dev ice, set the voltage rising time to have 50s or longer (between 0.2v and 2.7v) during power - on. ? notes during pll clock operation when the pll clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to o perate at the free running frequency of the self oscillator circuit built in the pll. this operation is not guaranteed. ? treatment of a/d converter power supply pins connect the pins to have avcc0 = avcc1 = avrh0 = avrh1 = vcc, avss0/avrl0 = avss1/avrl1 = vss even if the a/d converter is not used. ? note on using external clock the external clock is unsupported. external direct clock input cannot use.
document number: 002- 0466 5 rev * a page 36 of 175 mb91580m/s series ? power - on sequence of a/d converter power supply analog inputs be sure to turn on the digital power supply ( vcc5) first, and then turn on the a/d converter power supplies (avcc0, avcc1, avrh0, avrh1, avrl0, avrl1) and analog inputs (an0 to an14, an16 to an23). also, turn off the a/d converter power supplies (avcc0, avcc1, avrh0, avrh1, avrl0, avrl1) and analog i nputs (an0 to an14, an16 to an23) first, and then turn off the digital power supply (vcc5). when the avrh0 and avrh1 pin voltages are turned on or off, they must not exceed avcc0 and avcc1. even if a common analog input pin is used as an input port, its in put voltage must not exceed avcc0 or avcc1. (however, the analog power supply voltage and digital power supply voltage can be turned on or off simultaneously.) ? treatment of c pin this device contains a voltage step - down circuit. a capacitor must always be connected to the c pin to assure the internal stabilization of the device. for the standard values, see the "recommended operating conditions" of the latest data sheet. ? function switching of a multiplexed port to switch between the port function and the multiplexed pin function, use the pfr (port function register). for details, see "i/o ports" in hardware manual. ? low - power consumption mode to set sleep mode / watch mode / stop mode, or watch mode (power - off) / stop mode (power - off), see the section "la unching sleep mode / watch mode / stop mode" or "launching watch mode (power - off) / stop mode (power - off)" of "power consumption control" in hardware manual, and follow the procedures. do not perform the following when using a monitor debugger. ?do not se t a break point for the low - power consumption transition program. ?do not execute an operation step for the low - power consumption transition program. ? notes when writing data in a register having the status flag when writing data in the register that has a status flag (especially, an interrupt request flag) to control function, take care not to clear its status flag erroneously. the program must be written not to clear the flag to the status bit, and to set the control bits to have the desired value. espe cially, if multiple control bits are used, the bit instruction cannot be used. (the bit instruction can access to a single bit only.) the byte, half - word, or word access must be used to write data in the control bits and status flag simultaneously. during this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. note: these points can be ignored because the bit instructions already take the points into consideration for registers that support read - modify - write (rmw) operations. these points must be considered when using the bit instructions for registers that do not support rmw operations.
document number: 002- 0466 5 rev * a page 37 of 175 mb91580m/s series 7. block diagram ? mb91f583 a m/f584a m/f585 a m f r o m m a s t e r t o s l a v e f r o m m a s t e r t o s l a v e m d 0 , m d 1 ,p040 sot0_0-1 , sot1-3, daout nmix m o nc l k r x0- 1, t x0- 1 a i n 0-1 , b i n 0-1 , z i n 0- 1 i / o p o r t xbs c r o ss ba r s w i t c h f r 81 s c p u core i n s t r u c t i o n on-chip bus layer 2 peripheral bus bridge 1 6 3 2 wild register i / o p o r t on-chip bus layer 1 d ebug i n t e r f a c e regulator on-chip bus xb s m p u b a c k u p r a m dmac ramecc / power-on reset cr oscillator f l a s h r a m d a t a i nt 0- 7 mm dtti0,rto0-6 in0-3 a dt g0- 2 , a n 0- 14, 16-23 frck0-5 sin0_0-1, sin1-3, sck0_0-1, sck1-3, scs1-3 rstx diagnosis r x da - b,txda-b, t x ena - b,stopwt tioa 0-1 , t i ob 0-1 tin 0- 3 , tot 0- 3 trg 0- 1 , ppg 0- 5 main flash/workflash bus performance counter operating mode register bus bridge flexray (1unit) can (2ch) bus diagnosis register flash control register ramecc/diagnosis (xbs-ram) asynchronous bus bridge (pclk1 pclk2) asynchronous bus bridge (pclk1 pclk2) flexray clock control ppg (6ch) clock monitor can prescaler i/o port setting base timer (2ch) reload timer (4ch) u/d counter (2ch) wdt1 calibration 32-bit peripheral bus 16-bit peripheral bus crc (2ch) waveform generator (2 units (7ch)) output compare (7ch) a/d converter free-run timer (6ch) input capture (4ch) d/a converter multi-function serial interface (4ch) bus bridge (32-bit 16-bit) delay interrupt interrupt controller watchdog timer (sw and hw) interrupt request batch read generation/clear of dma transfer request clock control register (frequency dividing setting) reset control register low-power consumption setting register cr oscillation (trimming) nmi regulator control clock supervisor power shutdown control external interrupt input (8ch) clock control (clock setting, main timer, pll timer) low-voltage detection (internal low-voltage detection) low-voltage detection (external low-voltage detection) input cut-off inhibiting signal motor control extension function (pclk2 mtrclk)
document number: 002- 0466 5 rev * a page 38 of 175 mb91580m/s series ? mb91f583 a s/f584a s/f585a s f r o m m a s t e r t o s l a v e f r o m m a s t e r t o s l a v e m d 0 , m d 1 ,p040 sot0_0 , sot1, daout nmix m o nc l k r x0 , t x0 a i n 0-1 , b i n 0-1 , z i n 0- 1 i / o p o r t xbs c r o ss ba r s w i t c h f r 81 s c p u core i n s t r u c t i o n peripheral bus bridge 1 6 3 2 wild register i / o p o r t d ebug i n t e r f a c e on-chip bus xb s m p u b a c k u p r a m f l a s h r a m d a t a i nt 0- 6 mm dtti0,rto0-6 in0-3 a dt g0- 2 , a n 0- 14, 19, 20 frck0-5 sin0_0, sin1, sck0_0, sck1, scs1 rstx r x da - b,txda-b, t x ena - b,stopwt tioa 0-1 , t i ob 0-1 tin 0- 3 , tot 0- 3 trg 0- 1 , ppg 0- 5 main flash/workflash regulator cr oscillator power-on reset on-chip bus layer 2 on-chip bus layer 1 bus performance counter dmac operating mode register bus bridge flexray (1unit) can (1ch) bus diagnosis register flash control register ramecc/diagnosis (xbs-ram) ramecc / diagnosis flexray clock control ppg (6ch) clock monitor can prescaler i/o port setting base timer (2ch) reload timer (4ch) u/d counter (2ch) wdt1 calibration asynchronous bus bridge (pclk1 pclk2) asynchronous bus bridge (pclk1 pclk2) motor control extension function (pclk2 mtrclk) delay interrupt interrupt controller watchdog timer (sw and hw) interrupt request batch read generation/clear of dma transfer request clock control register (frequency dividing setting) reset control register low-power consumption setting register 32-bit peripheral bus 16-bit peripheral bus crc (2ch) waveform generator (2 units (7ch)) output compare (7ch) a/d converter free-run timer (6ch) input capture (4ch) d/a converter multi-function serial interface (2ch) bus bridge (32-bit 16-bit) input cut-off inhibiting signal cr oscillation (trimming) nmi regulator control clock supervisor power shutdown control external interrupt input (7ch) clock control (clock setting, main timer, pll timer) low-voltage detection (internal low-voltage detection) low-voltage detection (external low-voltage detection)
document number: 002- 0466 5 rev * a page 39 of 175 mb91580m/s series 8. memory map mb91 f 58 3am/f583as mb 91 f 58 4am / f 58 4as mb 91 f 58 5am / f585as 0000_0000 h 0000_0000 h 0000_0000 h 0000_4000 h b a ckup r am ( 8k b ) 0000_4000 h b a ckup r am ( 8k b ) 0000_4000 h b a ckup r am ( 8k b ) 0000_6000 h 0000_6000 h 0000_6000 h 0001_0000 h 0001_0000 h 0001_0000 h 0001_8000 h 0001_c000 h 0007_0000 h 0007_0000 h 0007_0000 h 000c_0000 h 000e_0000 h 0010_0000 h 0033_0000 h 0033_0000 h 0033_0000 h 0034_0000 h 0034_0000 h 0034_0000 h ffff_ffff h ffff_ffff h ffff_ffff h r eser v ed r eser v ed r eser v ed r eser v ed io area io area io area io area io area io area r eser v ed 0001_c000 h interrupt vector table reset vector table r eser v ed ram(32kb) ram(48kb) r eser v ed r eser v ed ram(48kb) r eser v ed interrupt vector table reset vector table 000f_fc00 h 000f_fc00 h 0010_0000 h r eser v ed 0010_0000 h interrupt vector table reset vector table r eser v ed 000f_fc00 h flash memory (256+64)kb flash memory (384+64)kb flash memory (512+64)kb workflash 64kb workflash 64kb workflash 64kb
document number: 002- 0466 5 rev * a page 40 of 175 mb91580m/s series 9. i/o map the following i/o map s hows the relationship between memory space and registers for peripheral resources. legend of i/o map the initial register value s after reset are indicate d as follows: "1": initial value "1" "0": initial value "0" "x": initial value undefined " - ": reserved bit/undefined bit "*": initial value "0" or "1" according to the setting note: it is prohibited to access addresses not described here. read/write attribute (r: read w: write) data access attribute b: byte h: half - word w: word (note) the access by the data access attribute not described is disabled. ini tial register value after reset address address offset value/register name block base timer 1 a/d converter 000090 h 00009 4 h 00009 8 h 00009 c h 0000 a 0 h 0000 a4 h 0000 a8 h + 0 + 1 + 2 + 3 bt1tmr [r] h 00000000 00000000 bt1tmcr [r/w] b,h,w 00000000 00000000 bt1stc [r/w] b 00000000 - - - - bt1pcsr/bt1prll [r/w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf [r/w] h 00000000 00000000 btsel [r/w] b ---- 0000 aderh [r/w] b, h, w 00000000 00000000 btsssr [w] b, h -------------- 11 aderl [r/w] b, h, w 00000000 00000000 adcs1 [r/w] b,h,w 0000 0000 adcs0 [r/w] b,h,w 00000000 adcr1 [r] b,h,w ------ xx adcr0 [r] b,h,w xxxxxxxx adct1 [r/w] b,h,w 00010000 adct0 [r/w] b,h,w 00101100 adsch [r/w] b,h,w --- 00000 adech [r/w] b,h,w --- 00000
document number: 002- 0466 5 rev * a page 41 of 175 mb91580m/s series ? mb91f583 a m/f584a m/f585 a m address address offset value/register name block +0 +1 +2 + 3 000000 h pdr00[r/w] b,h,w xxxxxxxx pdr01[r/w] b,h,w xxxxxxxx pdr02[r/w] b,h,w xxxxxxxx pdr03[r/w] b,h,w xxxxxxxx port data register 000004 h pdr04[r/w] b,h,w xxxxxxxx pdr05[r/w] b,h,w - xxxxxxx pdr06[r/w] b,h,w - xxxxxxx pdr07[r/w] b,h,w ----- xxx 000008 h pdr08[r/w] b,h,w xxxxxxxx pdr09[r/w] b,h,w xxxxxxxx pdr10[r/w] b,h,w ----- xxx - 00000c h - - - - 000010 h | 000038 h - - - - reserved 00003c h wdtcr0[r/w] b,h,w - 0 --0000 wdtcpr0[w] b,h,w 00000000 wdtcr1[r] b,h,w ----0010 wdtcpr1[w] b,h,w 00000000 watchd og timer [s] 000040 h - - - reserved 000044 h dicr[r/w] b -------0 - - - delay interrupt 000048 h | 00005c h - - reserved 000060 h tmrlra0[r/w] h xxxxxxxx xxxxxxxx tmr0[r] h xxxxxxxx xxxxxxxx reload timer 0 000064 h tmrlrb0[r/w] h xxxxxxxx xxxxxxxx tmcsr0[r /w] b,h,w 00000000 0- 000000 000068 h | 00007c h - - - - reserved 000080 h bt0tmr[r] h 00000000 00000000 bt0tmcr[r/w] h - 0000000 00000000 base timer 0 000084 h bt0tmcr2[r/w] b -------0 bt0stc[r/w] b - 0 - 0 - 0 - 0 - - 000088 h bt0pcsr/bt0prll[r/w] h 00000000 00000000 bt0pdut/bt0prlh/bt0dtbf [r/w] h 00000000 00000000 00008c h - - - - 000090 h bt1tmr[r] h 00000000 00000000 bt1tmcr[r/w] h - 0000000 00000000 base timer 1 000094 h bt1tmcr2[r/w] b -------0 bt1stc[r/w] b - 0 - 0 - 0 - 0 - - 000098 h bt1pcsr/bt1prll[r/w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf[r/w] h 00000000 00000000 00009c h btsel01[r/w] b ----0000 - btsssr[w] b,h -------- ------11 base timer 0,1
document number: 002- 0466 5 rev * a page 42 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0000a0 h | 0000fc h - - - - reserved 000100 h tmrlra1[r/w] h xxxxxxxx xxxxxxxx tmr1[r] h xxxxxxxx xxxxxxxx re load timer 1 000104 h tmrlrb1[r/w] h xxxxxxxx xxxxxxxx tmcsr1[r/w] b,h,w 00000000 0- 000000 000108 h tmrlra2[r/w] h xxxxxxxx xxxxxxxx tmr2[r] h xxxxxxxx xxxxxxxx reload timer 2 00010c h tmrlrb2[r/w] h xxxxxxxx xxxxxxxx tmcsr2[r/w] b,h,w 00000000 0- 000000 000110 h tmrlra3[r/w] h xxxxxxxx xxxxxxxx tmr3[r] h xxxxxxxx xxxxxxxx reload timer 3 000114 h tmrlrb3[r/w] h xxxxxxxx xxxxxxxx tmcsr3[r/w] b,h,w 00000000 0- 000000 000118 h | 00011c h - - - - reserved 000120 h irpr0h[r] b,h,w 00------ irpr0l[r] b,h,w 00------ irpr1h[r] b,h,w 00------ irpr1l[r] b,h,w -------- interrupt request batch read register 000124 h irpr2h[r] b,h,w -------- irpr2l[r] b,h,w *5 0000---- irpr3h[r] b,h,w 00------ irpr3l[r] b,h,w 00------ 000128 h irpr4h[r] b,h,w 00------ irpr4l[r] b,h,w 000000-- irpr5h[r] b,h,w 00------ irpr5l[r] b,h,w 00------ 00012c h irpr6h[r] b,h,w 0000---- irpr6l[r] b,h,w 00------ irpr7h[r] b,h,w 00------ irpr7l[r] b,h,w -------- 000130 h irpr8h[r] b,h,w -------- irpr8l[r] b,h,w 00------ irpr9h[r] b,h,w 00------ irpr 9l[r] b,h,w 00------ 000134 h irpr10h[r] b,h,w 00------ irpr10l[r] b,h,w 00------ irpr11h[r] b,h,w 00------ irpr11l[r] b,h,w 0000000- 000138 h irpr12h[r] b,h,w 0000000- irpr12l[r] b,h,w 00000000 irpr13h[r] b,h,w 0000000- irpr13l[r] b,h,w 00000000 00013c h irpr14h[r] b,h,w 00------ irpr14l[r] b,h,w 00------ irpr15h[r] b,h,w 00000000 irpr15l[r] b,h,w 0000---- 000140 h irpr16h[r] b,h,w 00------ irpr16l[r] b,h,w 00------ irpr17h[r] b,h,w 00------ irpr17l[r]b,h,w -------- 000144 h irpr18h[r] b,h,w ------- - irpr18l[r] b,h,w 000000-- - - 000148 h | 0001fc h - - - - reserved
document number: 002- 0466 5 rev * a page 43 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000200 h pcn0[r/w] b,h,w 00000000 000000- 0 pcsr0[w] h,w xxxxxxxx xxxxxxxx ppg0 000204 h pdut0[w] h,w xxxxxxxx xxxxxxxx ptmr0[r] h,w 11111111 11111111 000208 h pcn1[r/w] b,h,w 00000000 000000- 0 pcsr1[w] h,w xxxxxxxx xxxxxxxx ppg1 00020c h pdut1[w] h,w xxxxxxxx xxxxxxxx ptmr1[r] h,w 11111111 11111111 000210 h pcn2[r/w] b,h,w 00000000 000000- 0 pcsr2[w] h,w xxxxxxxx xxxxxxxx ppg2 000214 h pdut2[w] h,w xxxxxxxx xxxxxxxx ptmr2[r] h,w 11111111 11111111 000218 h pcn3[r/w] b,h,w 00000000 000000- 0 pcsr3[w] h,w xxxxxxxx xxxxxxxx ppg3 00021c h pdut3[w] h,w xxxxxxxx xxxxxxxx ptmr3[r] h,w 11111111 11111111 000220 h pcn4[r/w] b,h,w 00000000 000000- 0 pcsr4[w] h,w xxxxxxxx xxxxxxxx ppg4 000224 h pdut4[w ] h,w xxxxxxxx xxxxxxxx ptmr4[r] h,w 11111111 11111111 000228 h pcn5[r/w] b,h,w 00000000 000000- 0 pcsr5[w] h,w xxxxxxxx xxxxxxxx ppg5 00022c h pdut5[w] h,w xxxxxxxx xxxxxxxx ptmr5[r] h,w 11111111 11111111 000230 h | 0002bc h - - reserved 0002c0 h gtrs0[r/ w] b,h,w - 0000000 - 0000000 gtrs1[r/w] b,h,w - 0000000 - 0000000 ppg control 0002c4 h gtrs2[r/w] b,h,w - 0000000 - 0000000 - 0002c8 h - - 0002cc h - - 0002d0 h - - 0002d4 h - - 0002d8 h gtren0[r/w] h,w -------- --000000 - 0002dc h - - reserved 0002e0 h - gatec0[r/w] b,h,w ------00 - gatec2[r/w] b,h,w ------00 ppg gate control 0002e4 h - gatec4[r/w] b,h,w ------00 - - 0002e8 h - - - -
document number: 002- 0466 5 rev * a page 44 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0002ec h - - - - reserved 0002f0 h rcrh0[w] h,w 00000000 rcrl0[w] b,h,w 00000000 udcrh0[r] h,w 00000000 udcrl0[r] b,h,w 00000000 u/d counter 0 0002f4 h ccr0[r/w] b,h 00000000 - 0001000 - csr0[r] b 00000000 0002f8 h rcrh1[w] h,w 00000000 rcrl1[w] b,h,w 00000000 udcrh1[r] h,w 00000000 udcrl1[r] b,h,w 00000000 u/d counter 1 0002fc h ccr1[r/w] b,h 00000000 - 0001000 - csr1[r] b 00000000 000300 h - reserved 000304 h - - - - reserved 000308 h - reserved 00030c h - - - -
document number: 002- 0466 5 rev * a page 45 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000310 h - - mpucr[r/w] h 000000- 0 ----0100 mpu [s] (only the cpu can access this area) 000314 h - - - - 000318 h - 00031c h - - - 000320 h dpvar[r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000324 h - - dpvsr[r/w] h -------- 00000--0 000328 h dear[r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00032c h - - desr[r/w] h -------- 00000--0 000330 h pabr0[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000334 h - - pacr0[r/w] h 000000- 0 00000--0 000338 h pabr1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00033c h - - pacr1[r/w] h 000000- 0 00000--0 000340 h pabr2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000344 h - - pacr2[r/w] h 000000- 0 00000--0 000348 h pabr3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00034c h - - pacr3[r/w] h 000000- 0 00000--0 000350 h pabr4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000354 h - - pacr4[r/w] h 000000- 0 00000--0 000358 h pabr5[r/w] w xxxxxxxx xxxxxxxx x xxxxxxx xxxx0000 00035c h - - pacr5[r/w] h 000000- 0 00000--0 000360 h pabr6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000364 h - - pacr6[r/w] h 000000- 0 00000--0
document number: 002- 0466 5 rev * a page 46 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000368 h pabr7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 mpu [s] (only the cpu can access this area) 00036c h - - pacr7[r/w] h 000000- 0 00000--0 000370 h - reserved [s] 000374 h - - - 000378 h - 00037c h - - - 000380 h - 000384 h - - - 000388 h - 00038c h - - - 000390 h - 000394 h - - - reserved [s] 000398 h - 00039c h - - - 0003a0 h - 0003a4 h - - - 0003a8 h - 0003ac h - - - 0003b0 h | 0003cc h - - - - reserved [s] 0003d0 h - reserved [s] 0003d4 h - 0003d8 h - 0003dc h - 0003e0 h | 0003fc h - - - - reserved [s] 000400 h icsel0[r/w] b,h,w -----000 icsel1[r/w] b,h,w ------- 0 icsel2[r/w] b,h,w -------0 icsel3[r/w] b,h,w -------0 generation and clear of dma transfer request 000404 h icsel4[r/w] b,h,w -------0 icsel5[r/w] b,h,w -------0 icsel6[r/w] b,h,w -------0 icsel7[r/w] b,h,w -----000 000408 h icsel8[r/w] b,h,w -------0 icsel9[r/w] b,h,w -------0 icsel10[r/w] b,h,w ------00 icsel11[r/w] b,h,w -------0 00040c h icsel12[r/w] b,h,w -------0 icsel13[r/w] b,h,w -------0 icsel14[r/w] b,h,w -------0 icsel15[r/w] b,h,w -------0
document number: 002- 0466 5 rev * a page 47 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000410 h icsel16[r/w] b,h,w -------0 icsel 17[r/w] b,h,w -------0 icsel18[r/w] b,h,w -------0 icsel19[r/w] b,h,w -------0 generation and clear of dma transfer request 000414 h icsel20[r/w] b,h,w -------0 icsel21[r/w] b,h,w -----000 icsel22[r/w] b,h,w -----000 icsel23[r/w] b,h,w -----000 000418 h i csel24[r/w] b,h,w -----000 icsel25[r/w] b,h,w -----000 icsel26[r/w] b,h,w -------0 icsel27[r/w] b,h,w -------0 00041c h - - - - 000420 h - - - - 000424 h | 00043c h - - - - reserved 000440 h icr00[r/w] b,h,w ---11111 icr01[r/w] b,h,w ---11111 icr02[r/w] b,h,w ---11111 icr03[r/w] b,h,w ---11111 interrupt controller [s] 000444 h icr04[r/w] b,h,w ---11111 icr05[r/w] b,h,w ---11111 icr06[r/w] b,h,w ---11111 icr07[r/w] b,h,w ---11111 000448 h icr08[r/w] b,h,w ---11111 icr09[r/w] b,h,w ---11111 icr10[r/w] b,h, w ---11111 icr11[r/w] b,h,w ---11111 00044c h icr12[r/w] b,h,w ---11111 icr13[r/w] b,h,w ---11111 icr14[r/w] b,h,w ---11111 icr15[r/w] b,h,w ---11111 000450 h icr16[r/w] b,h,w ---11111 icr17[r/w] b,h,w ---11111 icr18[r/w] b,h,w ---11111 icr19[r/w] b,h,w ---11111 000454 h icr20[r/w] b,h,w ---11111 icr21[r/w] b,h,w ---11111 icr22[r/w] b,h,w ---11111 icr23[r/w] b,h,w ---11111 000458 h icr24[r/w] b,h,w ---11111 icr25[r/w] b,h,w ---11111 icr26[r/w] b,h,w ---11111 icr27[r/w] b,h,w ---11111 00045c h icr28[r/w ] b,h,w ---11111 icr29[r/w] b,h,w ---11111 icr30[r/w] b,h,w ---11111 icr31[r/w] b,h,w ---11111 000460 h icr32[r/w] b,h,w ---11111 icr33[r/w] b,h,w ---11111 icr34[r/w] b,h,w ---11111 icr35[r/w] b,h,w ---11111 000464 h icr36[r/w] b,h,w ---11111 icr37[r/w] b,h,w ---11111 icr38[r/w] b,h,w ---11111 icr39[r/w] b,h,w ---11111 000468 h icr40[r/w] b,h,w ---11111 icr41[r/w] b,h,w ---11111 icr42[r/w] b,h,w ---11111 icr43[r/w] b,h,w ---11111 00046c h icr44[r/w] b,h,w ---11111 icr45[r/w] b,h,w ---11111 icr46[r/w] b, h,w ---11111 icr47[r/w] b,h,w ---11111 000470 h | 00047c h - - - - reserved [s]
document number: 002- 0466 5 rev * a page 48 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000480 h rstrr[r] b,h,w xxxx -- xx rstcr[r/w] b,h,w 111----0 stbcr[r/w] b,h,w 000---11 * - reset control [s] power consumption control [s] * writing to stbcr by dma is disabled. 000484 h - - - - reserved [s] 000488 h divr0[r/w] b,h,w 000----- - divr2[r/w] b,h,w 0011---- - clock control [s] 00048c h - - - - reserved [s] 000490 h iorr0[r/w] b,h,w - 0000000 iorr1[r/w] b,h,w - 0000000 iorr2[r/w] b,h,w - 0000000 iorr3[r/w] b,h,w - 0000000 dma transfer request from a peripheral [s] 000494 h iorr4[r/w] b,h,w - 0000000 iorr5[r/w] b,h,w - 0000000 iorr6[r/w] b,h,w - 0000000 iorr7[r/w] b,h,w - 0000000 000498 h - - - - 00049c h - - - - 0004a0 h - - - - reserved 0004a4 h canpre[r/w] b,h,w ---00000 - - - can prescaler 0004a8 h | 0004ac h - - - - reserved 0004b0 h - - - - reserved 0004b4 h | 0004c0 h - - - - reserved 0004c4 h cucr1[r/w] b,h,w -------- ---0 --00 cutd1[r/w] b,h,w 11000011 01010000 wdt1 calibration 0004c8 h cutr1[r] b,h,w -------- 00000000 0 0000000 00000000 0004cc h | 0004dc h - - - - reserved 0004e0 h - - cscfg[r/w] b,h,w ---0 ---- cmcfg[r/w] b,h,w 00000000 clock monitor 0004e4 h - - - - 0004e8 h pll2divm[r/w] b,h,w ----0000 pll2divn[r/w] b,h,w - 0000000 pll2divg[r/w] b,h,w ----0000 pll2mulg[ r/w] b,h,w 00000000 flexray clock control *5 0004ec h pll2ctrl[r/w] b,h,w ----0000 pll2divk[r/w] b,h,w -------0 clkr2[r/w] b,h,w 000--000 -
document number: 002- 0466 5 rev * a page 49 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0004f0 h | 0004fc h - - - - reserved 000500 h - reserved 000504 h - reserved 000508 h | 00050c h - - - - reserved 000510 h cselr[r/w] b,h,w - 0 ----00 cmonr[r] b,h,w - 01---00 mtmcr[r/w] b,h,w 00001111 - clock control [s] 000514 h pllcr[r/w] b,h,w 00- 00000 11110000 cstbr[r/w] b,h,w ----0000 ptmcr[r/w] b,h,w 00------ 000518 h - - cpuar[r/w] b,h,w 0 --- xxxx - reset [s] 00051c h - - - reserved [s] 000520 h ccpsselr[r/w] b,h,w -------0 - - ccpsdivr[r/w] b,h,w - 000- 000 clock control 2 000524 h - ccpllfbr[r/w] b,h,w - 0000000 ccssfbr0[r/w] b,h,w --000000 ccssfbr1[r/w] b,h,w ---00000 000528 h - ccssccr0[r/w] b,h,w ----0000 ccssccr1 [r/w] b,h,w 000----- -------- 00052c h - cccgrcr0[r/w] b,h,w 00----00 cccgrcr1[r/w] b,h,w 00000000 cccgrcr2[r/w] b,h,w 00000000 000530 h - - ccpmucr0[r/w] b,h,w 0 -----00 ccpmucr1[r/w] b,h,w 0 --00000 000534 h - - - - 000538 h - - - - 00053c h - - - - 000540 h | 00054c h - - - - reserved 000550 h eirr0[r/w] b,h,w xxxxxxxx enir0[r/w] b,h,w 00000000 elvr0[r/w] b,h,w 00000000 00000000 external interrupt (int0 to 7) 000554 h | 000568 h - - - - reserved 00056c h - csvcr[r/w] b - 0 --1 --0 - - csv
document number: 002- 0466 5 rev * a page 50 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000570 h crtr[r /w] b,h,w 01111111 - - - wdt1 calibration (trimming) 000574 h | 00057c h - - - - reserved 000580 h regsel[r/w] b,h,w 01--110- - - - regulator control 000584 h lvd5r[r/w] b,h,w -------1 lvd5f[r/w] b,h,w 001100- 1 lvd[r/w] b,h,w 01000--0 - low - voltage detecti on 000588 h | 00058c h - - - - reserved 000590 h pmustr [r/w] b,h,w 0 -----1x pmuctlr[r/w] b,h,w 0 - 00---- pwrtmctl[r/w] b,h,w -----011 - pmu 000594 h - pmuintf1[r/w] b,h,w 00000000 pmuintf2[r/w] b,h,w - 00----- - 000598 h - - - - 00059c h - - - - 0005a0 h | 0005fc h - - - - reserved 000600 h | 00060c h - - - - reserved [s] 000610 h | 00063c h - - - - reserved [s] 000640 h | 00064c h - - - - reserved [s] 000650 h | 00067c h - - - - reserved [s] 000680 h | 00068c h - - - - reserved [s] 000690 h | 0006bc h - - - - re served [s]
document number: 002- 0466 5 rev * a page 51 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0006c0 h | 0006cc h - - - - reserved [s] 0006d0 h | 0006f0 h - - - - reserved 0006f4 h - reserved 0006f8 h | 0006fc h - - - - reserved 000700 h - reserved 000704 h | 00070c h - - - - reserved 000710 h bpccra[r/w] b 00000000 bpccrb[r/w] b 00000000 bp ccrc[r/w] b 00000000 - bus performance counter 000714 h bpctra[r/w] w 00000000 00000000 00000000 00000000 000718 h bpctrb[r/w] w 00000000 00000000 00000000 00000000 00071c h bpctrc[r/w] w 00000000 00000000 00000000 00000000 000720 h | 0007f8 h - - - - re served 0007fc h bmodr[r] b,h,w xxxxxxxx - - - operation mode 000800 h | 00083c h - - - - reserved [s] 000840 h fctlr[r/w] h - 0 -- 1000 0--0 ---- - fstr[r/w] b -----001 flash memory register [s] 000844 h - - - - reserved [s] 000848 h | 000854 h - - - - reserved [s] 000858 h - - wren[r/w] h 00000000 00000000 wild register [s] 00085c h | 00087c h - - - - reserved [s]
document number: 002- 0466 5 rev * a page 52 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000880 h wrar00[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 000884 h wrdr00[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000888 h wrar01[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00088c h wrdr01[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000890 h wrar02[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 000894 h wrdr02[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000898 h wrar03[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00089c h wrdr03[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a0 h wrar04[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008a4 h wrdr04[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a8 h wrar05[r/w] w -------- -- xxxxx x xxxxxxxx xxxxxx -- 0008ac h wrdr05[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b0 h wrar06[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008b4 h wrdr06[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b8 h wrar07[r/w] w -------- -- xxxxxx xxxxxxxx xxxxx x -- 0008bc h wrdr07[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c0 h wrar08[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008c4 h wrdr08[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c8 h wrar09[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008cc h wr dr09[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
document number: 002- 0466 5 rev * a page 53 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0008d0 h wrar10[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 0008d4 h wrdr10[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d8 h wrar11[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008dc h wrdr11[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e0 h wrar12[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008e4 h wrdr12[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e8 h wrar13[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ec h wrdr13[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f0 h wrar14[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008f4 h wrdr14[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f8 h wrar15[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008fc h wrdr15[r/w] w xxxxxxxx xxxxx xxx xxxxxxxx xxxxxxxx 000900 h | 000bf8 h - - - - reserved 000bfc h - uer[w] b,h,w -------- ------- x ocdu
document number: 002- 0466 5 rev * a page 54 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000c00 h dccr0[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 dma controller [s] 000c04 h dcsr0[r/w] h 0 ------- ----- 000 dtcr0[r/w] h 00000000 00000000 000c08 h dsar0[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c0c h ddar0[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c10 h dccr1[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c14 h dcsr1[r/w] h 0 ------- ----- 000 dtcr1[r/w] h 00000000 00000000 000c18 h dsar1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c1c h ddar1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c20 h dccr2[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c24 h dcsr2[r/w] h 0 ------- ----- 000 dtcr2[r/w] h 00000000 00000000 000c28 h dsar2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c2c h ddar2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c30 h dccr3[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c34 h dcsr3[r/w] h 0 ------- ----- 000 dtcr3[r/w] h 00000000 00000000 000c 38 h dsar3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c3c h ddar3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c40 h dccr4[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c44 h dcsr4[r/w] h 0 ------- ----- 000 dtcr4[r/w] h 00000000 00000000
document number: 002- 0466 5 rev * a page 55 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0 00c48 h dsar4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dma controller [s] 000c4c h ddar4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c50 h dccr5[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c54 h dcsr5[r/w] h 0 ------- ----- 000 dtcr5[r/w] h 00000000 00000000 000c58 h dsar5[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c5c h ddar5[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c60 h dccr6[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c64 h dcsr6[r/w] h 0 ------- ----- 000 dtcr6[r/w] h 00000000 00000000 000c68 h dsar6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c6c h ddar6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c70 h dccr7[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c74 h dcsr7[r/w] h 0 ------- ----- 000 dtcr7[r/w] h 00000000 00000000 000c 78 h dsar7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c7c h ddar7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c80 h | 000df0 h - - - - 000df4 h - - dnmir[r/w] b 0 ------0 dilvr[r/w] b ---11111 000df8 h dmacr[r/w] w 0 ------- -------- 0 ------- -------- 000dfc h - - - - reserved [s] 000e00 h ddr00[r/w] b,h 00000000 ddr01[r/w] b,h 00000000 ddr02[r/w] b,h 00000000 ddr03[r/w] b,h 00000000 data direction register 000e04 h ddr04[r/w] b,h 00000000 ddr05[r/w] b,h - 0000000 ddr06[r/w] b,h - 0000000 ddr07[r/w] b,h -----000 000e08 h ddr08[r/w] b,h 00000000 ddr09[r/w] b,h 00000000 ddr10[r/w] b,h -----000 - 000e0c h - - - -
document number: 002- 0466 5 rev * a page 56 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000e10 h | 000e1c h - - - - reserved 000e20 h pfr00[r/w] b,h 00000000 pfr01[r/w] b,h 00000000 pfr02[r/w] b,h 00000000 pfr03[r/w] b,h 00000000 po rt function register 000e24 h pfr04[r/w] b,h 00000000 pfr05[r/w] b,h - 0000000 pfr06[r/w] b,h - 0000000 pfr07[r/w] b,h -----000 000e28 h pfr08[r/w] b,h 00000000 pfr09[r/w] b,h 00000000 pfr10[r/w] b,h -----000 - 000e2c h - - - - 000e30 h | 000e3c h - - - - reserved 000e40 h pddr00[r] b,h,w xxxxxxxx pddr01[r] b,h,w xxxxxxxx pddr02[r] b,h,w xxxxxxxx pddr03[r] b,h,w xxxxxxxx input data direct read register 000e44 h pddr04[r] b,h,w xxxxxxxx pddr05[r] b,h,w - xxxxxxx pddr06[r] b,h,w - xxxxxxx pddr07[r] b,h,w ----- xxx 000e48 h pddr08[r] b,h,w xxxxxxxx pddr09[r] b,h,w xxxxxxxx pddr10[r] b,h,w ----- xxx - 000e4c h - - - - 000e50 h | 000e5c h - - - - reserved 000e60 h epfr00[r/w] b,h ------00 epfr01[r/w] b,h ---00000 epfr02[r/w] b,h --000000 epfr03[r/w] b,h --000000 e xtended port function register 000e64 h - - epfr06[r/w] b,h ------00 epfr07[r/w] b,h ----0000 000e68 h epfr08[r/w] b,h *5 ----0000 epfr09[r/w] b,h -------0 epfr10[r/w] b,h - 0000000 - 000e6c h - - epfr14[r/w] b,h --0 - 0 - 0 - - 000e70 h - - - - 000e74 h - - - - 000e78 h - - - - 000e7c h - - - - 000e80 h - - - - 000e84 h | 000ebc h - - - - reserved
document number: 002- 0466 5 rev * a page 57 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000ec0 h pper00[r/w] b,h 00000000 pper01[r/w] b,h 00000000 pper02[r/w] b,h 00000000 pper03[r/w] b,h 00000000 port pull - up/down enable register 000ec4 h pper04[r/w] b,h 00000000 pper05[r/w] b,h - 0000000 pper06[r/w] b,h - 0000000 pper07[r/w] b,h -----000 000ec8 h pper08[r/w] b,h 00000000 pper09[r/w] b,h 00000000 pper10[r/w] b,h -----000 - 000ecc h - - - - 000ed0 h | 000edc h - - - - reserved 000ee0 h pilr0 0[r/w] b,h 11111111 pilr01[r/w] b,h 11111111 pilr02[r/w] b,h 11111111 pilr03[r/w] b,h 11111111 port input level selection register 000ee4 h pilr04[r/w] b,h 11111111 pilr05[r/w] b,h - 1111111 pilr06[r/w] b,h - 1111111 pilr07[r/w] b,h -----111 000ee8 h pilr08 [r/w] b,h 11111111 pilr09[r/w] b,h 11111111 pilr10[r/w] b,h -----111 - 000eec h - - - - 000ef0 h | 000efc h - - - - reserved 000f00 h | 000f1c h - - - - reserved 000f20 h podr00[r/w] b,h 00000000 podr01[r/w] b,h 00000000 podr02[r/w] b,h 00000000 podr03[r/w ] b,h 00000000 port output drive register 000f24 h podr04[r/w] b,h 00000000 podr05[r/w] b,h - 0000000 podr06[r/w] b,h - 0000000 podr07[r/w] b,h -----000 000f28 h podr08[r/w] b,h 00000000 podr09[r/w] b,h 00000000 podr10[r/w] b,h -----000 - 000f2c h - - - - 000f30 h | 000f3c h - - - - reserved 000f40 h porten[r/w] b,h,w ------00 - - - port input enable register 000f44 h keycdr[r/w] h 00000000 00000000 - - port key code 000f48 h aderh[r/w] b,h -------- 11111111 aderl[r/w] b,h - 1111111 11111111 analog input ena ble register 000f4c h daer[r/w] b,h -------0 - - - analog output enable register
document number: 002- 0466 5 rev * a page 58 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 000f50 h | 000ffc h - - - - reserved 001000 h sacr[r/w] b,h,w -------0 picd[r/w] b,h,w ----0011 - - synchronous/asyn chronous switch control 001004 h | 0010bc h - - - - reserved 0010c0 h - - - crccr[r/w] b,h,w - 0000000 crc arithmetic operation 0 0010c4 h crcinit[r/w] b,h,w 11111111 11111111 11111111 11111111 0010c8 h crcin[r/w] b,h,w 00000000 00000000 00000000 00000000 0010cc h crcr[r] b,h,w 11111111 11111111 11111111 11111111 0010d0 h - - - crccr1[r/w] b,h,w - 0000000 crc arithmetic operation 1 0010d4 h crcinit1[r/w] b,h,w 11111111 11111111 11111111 11111111 0010d8 h crcin1[r/w] b,h,w 00000000 00000000 00000000 00000000 0010dc h crcr1[r] b,h,w 11111111 11111111 11111111 11111 111 0010e0 h | 0010fc h - - - - reserved 001100 h tcgs[r/w] b,h,w ------00 - - tcgse[r/w] b,h,w --000000 free - run timer simultaneous activation 001104 h cpclrb0/cpclr0[r/w] h,w 11111111 11111111 tcdt0[r/w] h,w 00000000 00000000 free - run timer 0 001108 h tc cs0[r/w] b,h,w 00000000 01000000 ----0000 -------- 00110c h cpclrb1/cpclr1[r/w] h,w 11111111 11111111 tcdt1[r/w] h,w 00000000 00000000 free - run timer 1 001110 h tccs1[r/w] b,h,w 00000000 01000000 ----0000 -------- 001114 h cpclrb2/cpclr2[r/w] h,w 11111111 11111111 tcdt2[r/w] h,w 00000000 00000000 free - run timer 2 001118 h tccs2[r/w] b,h,w 00000000 01000000 ----0000 --------
document number: 002- 0466 5 rev * a page 59 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00111c h cpclrb3/cpclr3[r/w] h,w 11111111 11111111 tcdt3[r/w] h,w 00000000 00000000 free - run timer 3 001120 h tccs3[r/w] b,h,w 00000000 01000000 ----0000 -------- 001124 h cpclrb4/cpclr4[r/w] h,w 11111111 11111111 tcdt4[r/w] h,w 00000000 00000000 free - run timer 4 001128 h tccs4[r/w] b,h,w 00000000 01000000 ----0000 -------- 00112c h cpclrb5/cpclr5[r/w] h,w 11111111 11111111 tcdt5[r/w ] h,w 00000000 00000000 free - run timer 5 001130 h tccs5[r/w] b,h,w 00000000 01000000 ----0000 -------- 001134 h frs0[r/w] b,h,w -------- - 000- 000 - 000- 000 - 000 - 000 free - run timer selection 001138 h frs1[r/w] b,h,w -------- -------- - 000- 000 - 000- 000 00113c h frs2[r/w] b,h,w -------- - 000- 000 - 000- 000 - 000 - 000 001140 h - 001144 h frs4[r/w] b,h,w - 000- 000 - 000- 000 - 000- 000 - 000- 000 001148 h frs5[r/w] b,h,w -----000 - 000- 000 - 000- 000 - 000- 000 00114c h frs6[r/w] b,h,w - 000- 000 - 000- 000 - 000- 000 - 000- 000 001150 h - 001154 h occpb0/occp0[r/w] h,w 00000000 00000000 occpb1/occp1[r/w] h,w 00000000 00000000 output compare 0/1 001158 h ocs01[r/w] b,h,w - 110--00 00001100 - ocmod01[r/w] b,h,w ------00 00115c h occpb2/occp2[r/w] h,w 00000000 00000000 occpb3/occp3 [r/w] h,w 00000000 00000000 output compare 2/3 001160 h ocs23[r/w] b,h,w - 110--00 00001100 - ocmod23[r/w] b,h,w ------00 001164 h occpb4/occp4[r/w] h,w 00000000 00000000 occpb5/occp5[r/w] h,w 00000000 00000000 output compare 4/5 001168 h ocs45[r/w] b,h,w - 110--00 00001100 - ocmod45[r/w] b,h,w ------00
document number: 002- 0466 5 rev * a page 60 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00116c h occpb6/occp6[r/w] h,w 00000000 00000000 occpb7/occp7[r/w] h,w 00000000 00000000 output compare 6/7 001170 h ocs67[r/w] b,h,w - 110--00 00001100 - ocmod67[r/w] b,h,w ------00 001174 h occpb8/o ccp8[r/w] h,w 00000000 00000000 occpb9/occp9[r/w] h,w 00000000 00000000 output compare 8/9 001178 h ocs89[r/w] b,h,w - 110--00 00001100 - ocmod89[r/w] b,h,w ------00 00117c h occpb10/occp10[r/w] h,w 00000000 00000000 occpb11/occp11[r/w] h,w 00000000 00000000 output compare 10/11 001180 h ocs1011[r/w] b,h,w - 110--00 00001100 - ocmod1011 [r/w] b,h,w ------00 001184 h ipcp0[r] h,w 00000000 00000000 ipcp1[r] h,w 00000000 00000000 input capture 0/1 001188 h ics01[r/w] b,h,w ------ 00 00000000 - lsyns[r/w] b,h,w ----0000 00118c h ipcp2[r] h,w 00000000 00000000 ipcp3[r] h,w 00000000 00000000 input capture 2/3 001190 h ics23[r/w] b,h,w ------ 00 00000000 - - 001194 h - - reserved 001198 h - - - 00119c h - - reserved 0011a0 h - - - 0011a4 h dtsr[r/w] b,h,w ------10 - - - dtti selection 0011a8 h tmrr0[r/w] h,w 00000000 00000001 tmrr1[r/w] h,w 00000000 00000001 waveform generator 0/1/2 0011ac h tmrr2[r/w] h,w 00000000 00000001 - - 0011b0 h dtscr0[r/w] b,h,w 00000000 dtscr1[r/w] b,h,w 00000000 dtscr2[r/w] b,h,w 00000000 - 0011b4 h - dtir0[r/w] b,h,w 000000-- - dtmns0[r/w] b,h,w 00---000 0011b8 h - sigcr10[r/w] b,h,w 00000000 - sigcr20[r/w] b,h,w 000000- 1 0011bc h pics0[r/w] b,h,w 000000-- -------- -------- --------
document number: 002- 0466 5 rev * a page 61 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0011c0 h tmrr3[r/w] h,w 00000000 00000001 t mrr4[r/w] h,w 00000000 00000001 waveform generator 3/4/5 0011c4 h tmrr5[r/w] h,w 00000000 00000001 - - 0011c8 h dtscr3[r/w] b,h,w 00000000 dtscr4[r/w] b,h,w 00000000 dtscr5[r/w] b,h,w 00000000 - 0011cc h - dtir1[r/w] b,h,w 000000-- - dtmns1[r/w] b,h,w 00---000 waveform generator 3/4/5 0011d0 h - sigcr11[r/w] b,h,w 00000000 - sigcr21[r/w] b,h,w -------1 0011d4 h - 0011d8 h - - - - 12- bit a/d converter 0011dc h adtss[r/w] b,h,w -------0 - - - 0011e0 h adtse[r/w] b,h,w -------- 00000000 - 0000000 00000000 0011e4 h adcomp0/adcompb0[r/w] h,w 00000000 00000000 adcomp1/adcompb1[r/w] h,w 00000000 00000000 0011e8 h adcomp2/adcompb2[r/w] h,w 00000000 00000000 adcomp3/adcompb3[r/w] h,w 00000000 00000000 0011ec h adcomp4/adcompb4[r/w] h,w 00000000 00000000 adcomp 5/adcompb5[r/w] h,w 00000000 00000000 0011f0 h adcomp6/adcompb6[r/w] h,w 00000000 00000000 adcomp7/adcompb7[r/w] h,w 00000000 00000000 0011f4 h adcomp8/adcompb8[r/w] h,w 00000000 00000000 adcomp9/adcompb9[r/w] h,w 00000000 00000000 0011f8 h adcomp10/adc ompb10[r/w] h,w 00000000 00000000 adcomp11/adcompb11[r/w] h,w 00000000 00000000 0011fc h adcomp12/adcompb12[r/w] h,w 00000000 00000000 adcomp13/adcompb13[r/w] h,w 00000000 00000000 001200 h adcomp14/adcompb14[r/w] h,w 00000000 00000000 - 001204 h adcomp 16/adcompb16[r/w] h,w 00000000 00000000 adcomp17/adcompb17[r/w] h,w 00000000 00000000 001208 h adcomp18/adcompb18[r/w] h,w 00000000 00000000 adcomp19/adcompb19[r/w] h,w 00000000 00000000 00120c h adcomp20/adcompb20[r/w] h,w 00000000 00000000 adcomp21/adc ompb21[r/w] h,w 00000000 00000000 001210 h adcomp22/adcompb22[r/w] h,w 00000000 00000000 adcomp23/adcompb23[r/w] h,w 00000000 00000000 001214 h - - - -
document number: 002- 0466 5 rev * a page 62 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 001218 h - - - - 12- bit a/d converter 00121c h - - - - 001220 h - - - - 001224 h adtcs0[r/ w] b,h,w 00000000 0010- 000 adtcs1[r/w] b,h,w 00000000 0010- 000 001228 h adtcs2[r/w] b,h,w 00000000 0010- 000 adtcs3[r/w] b,h,w 00000000 0010- 000 00122c h adtcs4[r/w] b,h,w 00000000 0010- 000 adtcs5[r/w] b,h,w 00000000 0010- 000 001230 h adtcs6[r/w] b,h,w 0 0000000 0010 - 000 adtcs7[r/w] b,h,w 00000000 0010- 000 001234 h adtcs8[r/w] b,h,w 00000000 0010- 000 adtcs9[r/w] b,h,w 00000000 0010- 000 001238 h adtcs10[r/w] b,h,w 00000000 0010- 000 adtcs11[r/w] b,h,w 00000000 0010- 000 00123c h adtcs12[r/w] b,h,w 00000000 0010- 000 adtcs13[r/w] b,h,w 00000000 0010- 000 001240 h adtcs14[r/w] b,h,w 00000000 0010- 000 - 001244 h adtcs16[r/w] b,h,w 00000000 00100000 adtcs17[r/w] b,h,w 00000000 00100000 001248 h adtcs18[r/w] b,h,w 00000000 00100000 adtcs19[r/w] b,h,w 00000000 00100000 00124c h adtcs20[r/w] b,h,w 00000000 00100000 adtcs21[r/w] b,h,w 00000000 00100000 001250 h adtcs22[r/w] b,h,w 00000000 00100000 adtcs23[r/w] b,h,w 00000000 00100000 001254 h - - - - 001258 h - - - - 00125c h - - - - 001260 h - - - - 001264 h adtcd0[r] b,h,w 10--0000 00000000 adtcd1[r] b,h,w 10--0000 00000000 001268 h adtcd2[r] b,h,w 10--0000 00000000 adtcd3[r] b,h,w 10--0000 00000000 00126c h adtcd4[r] b,h,w 10--0000 00000000 adtcd5[r] b,h,w 10--0000 00000000 001270 h adtcd6[r] b,h,w 10--0000 00000000 adtcd7[r] b,h,w 10--0000 00000000 001274 h adtcd8[r] b,h,w 10--0000 00000000 adtcd9[r] b,h,w 10--0000 00000000
document number: 002- 0466 5 rev * a page 63 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 001278 h adtcd10[r] b,h,w 10--0000 00000000 adtcd11[r] b,h,w 10--0000 00000000 12- bit a/d converter 00127c h adtcd12[r] b,h ,w 10--0000 00000000 adtcd13[r] b,h,w 10--0000 00000000 001280 h adtcd14[r] b,h,w 10--0000 00000000 - 001284 h adtcd16[r] b,h,w 10--0000 00000000 adtcd17[r] b,h,w 10--0000 00000000 001288 h adtcd18[r] b,h,w 10--0000 00000000 adtcd19[r] b,h,w 10--0000 00000000 00128c h adtcd20[r] b,h,w 10--0000 00000000 adtcd21[r] b,h,w 10--0000 00000000 001290 h adtcd22[r] b,h,w 10--0000 00000000 adtcd23[r] b,h,w 10--0000 00000000 001294 h - - - - 001298 h - - - - 00129c h - - - - 0012a0 h - - - - 0012a4 h adcs0[r /w] b,h,w 0 ------- -------- adch0[r] b,h,w -----000 admd0[r/w] b,h,w ----0000 0012a8 h adcs1[r/w] b,h,w 0 ------- -------- adch1[r] b,h,w -----000 admd1[r/w] b,h,w ----0000 0012ac h adcs2[r/w] b,h,w 0 ------- -------- adch2[r] b,h,w -----000 admd2[r/w] b,h ,w ----0000 0012b0 h mtrcsr[r/w] b,h,w -------0 - - - motor control extension function 0012b4 h rtosel0[r/w] b,h,w --000000 rtosel1[r/w] b,h,w -------0 - - 0012b8 h | 0012fc h - - - - reserved 001300 h - - - - reserved 001304 h - - - - 001308 h - - - - 00130c h - - - - 001310 h - - - - 001314 h - - - - 001318 h - - - - 00131c h - - - - 001320 h - - - - 001324 h - -
document number: 002- 0466 5 rev * a page 64 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 001328 h | 00132c h - - - - reserved 001330 h - - 001334 h | 0013fc h - - - - reserved 001400 h dacr[r/w] b,h,w -------0 - dadr[r/w] h, w ------ xx xxxxxxxx dac 001404 h | 0014fc h - - - - reserved 001500 h scr0/(ibcr0) [r/w] b,h,w 0 --00000 smr0[r/w] b,h,w 000000- 0 ssr0[r/w] b,h,w 0 --00011 escr0/(ibsr0) [r/w] b,h,w 00000000 multi function serial i/f 0 *1 : byte access is possible only for ac cess to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset *3 : reserved because csio mode is not set immediately after reset *4 : reserved because lin2.1 mode is not set immediately after reset 001504 h - /(rdr10/(tdr10))[r/w] b,h ,w -------- -------- *3 rdr00/(tdr00)[r/w] b,h,w ------- 0 00000000 *1 001508 h sacsr0[r/w] b,h,w 0 ----000 00000000 stmr0[r] b,h,w 00000000 00000000 00150c h stmcr0[r/w] b,h,w 00000000 00000000 - /(sfur0) [r/w] b,h,w -------- -------- *4 001510 h - - - /(s flr10) [r/w] b,h,w -------- *4 - /(sflr00) [r/w] b,h,w -------- *4 001514 h - - - - 001518 h - - - - 00151c h bgr0[r/w] h,w 00000000 00000000 - /(ismk0)[r/w] b,h,w -------- *2 - /(isba0)[r/w] b,h,w -------- *2 001520 h fcr10[r/w] b,h,w 00- 00100 fcr00[ r/w ] b,h,w - 0000000 fbyte20[r/w] b,h,w 00000000 fbyte10[r/w] b,h,w 00000000
document number: 002- 0466 5 rev * a page 65 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 001524 h scr1[r/w] b,h,w 0 --00000 smr1[r/w] b,h,w 000000- 0 ssr1[r/w] b,h,w 0 --00011 escr1[r/w] b,h,w 00000000 multi function serial i/f 1 *1 : byte access is possib le only for access to lower 8 bits. *3 : reserved because csio mode is not set immediately after reset *4 : reserved because lin2.1 mode is not set immediately after reset 001528 h - /(rdr11/(tdr11))[r/w] b,h,w -------- -------- *3 rdr01/(tdr01)[r/w] b,h,w ------- 0 00000000 *1 00152c h sacsr1[r/w] b,h,w 0 ----000 00000000 stmr1[r] b,h,w 00000000 00000000 001530 h stmcr1[r/w] b,h,w 00000000 00000000 - /(scscr1/sfur1) [r/w] b,h,w -------- -------- *3 *4 001534 h - /(scstr31) [r/w] b,h,w -------- *3 - /(scstr21) [ r/w] b,h,w -------- *3 - / (scstr11/ sflr11) [r/w] b,h,w -------- *3 *4 - /(scstr01/ sflr01) [r/w] b,h,w -------- *3 *4 001538 h - - - - 00153c h - - - tbyte0 1 [r/w] b,h,w 00000000 001540 h bgr1[r/w] h,w 00000000 00000000 - - 001544 h fcr11[r/w] b,h,w 00- 0 0100 fcr01[ r/w ] b,h,w - 0000000 fbyte21[r/w] b,h,w 00000000 fbyte11[r/w] b,h,w 00000000 001548 h scr2/(ibcr2) [r/w] b,h,w 0 --00000 smr2[r/w] b,h,w 000000- 0 ssr2[r/w] b,h,w 0 --00011 escr2/(ibsr2) [r/w] b,h,w 00000000 multi function serial i/f 2 *1 : byte ac cess is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset *3 : reserved because csio mode is not set immediately after reset *4 : reserved because lin2.1 mode is not set immediately after reset 00154c h - /(rdr12/(tdr12))[r/w] b,h,w -------- -------- *3 rdr02/(tdr02)[r/w] b,h,w ------- 0 00000000 *1 001550 h sacsr2[r/w] b,h,w 0 ----000 00000000 stmr2[r] b,h,w 00000000 00000000 001554 h stmcr2[r/w] b,h,w 00000000 00000000 - /(scscr2/sfur2) [r/w] b,h,w ---- ---- -------- *3 *4 001558 h - /(scstr32) [r/w] b,h,w -------- *3 - /(scstr22) [r/w] b,h,w -------- *3 - /(scstr12/ sflr12) [r/w] b,h,w -------- *3 *4 - /(scstr02/ sflr02) [r/w] b,h,w -------- *3 *4 00155c h - - - - 001560 h - - - tbyte02[r/w] b,h,w 00000000 001564 h bgr2[r/w] h,w 00000000 00000000 - /(ismk2)[r/w] b,h,w -------- *2 - /(isba2)[r/w] b,h,w -------- *2 001568 h fcr12[r/w] b,h,w 00- 00100 fcr02[ r/w ] b,h,w - 0000000 fbyte22[r/w] b,h,w 00000000 fbyte12[r/w] b,h,w 00000000
document number: 002- 0466 5 rev * a page 66 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00156c h scr3/(ibcr 3) [r/w] b,h,w 0 --00000 smr3[r/w] b,h,w 000000- 0 ssr3[r/w] b,h,w 0 --00011 escr3/(ibsr3) [r/w] b,h,w 00000000 multi function serial i/f 3 *1 : byte access is possible only for access to lower 8 bits. *2 : reserved because i 2 c mode is not set immediately afte r reset *3 : reserved because csio mode is not set immediately after reset *4 : reserved because lin2.1 mode is not set immediately after reset 001570 h - /(rdr13/(tdr13))[r/w] b,h,w -------- -------- *3 rdr03/(tdr03)[r/w] b,h,w ------- 0 00000000 *1 001574 h sacsr3[r/w] b,h,w 0 ----000 00000000 stmr3[r] b,h,w 00000000 00000000 001578 h stmcr3[r/w] b,h,w 00000000 00000000 - /(scscr3/sfur3) [r/w] b,h,w -------- -------- *3 *4 00157c h - /(scstr33) [r/w] b,h,w -------- *3 - /(scstr23) [r/w] b,h,w -------- *3 - /(sc str13/ sflr13) [r/w] b,h,w -------- *3 *4 - /(scstr03/ sflr03) [r/w] b,h,w -------- *3 *4 001580 h - - - - 001584 h - - - tbyte03[r/w] b,h,w 00000000 001588 h bgr3[r/w] h,w 00000000 00000000 - /(ismk3)[r/w] b,h,w -------- *2 - /(isba3)[r/w] b,h,w -------- *2 00158c h fcr13[r/w] b,h,w 00- 00100 fcr03[ r/w ] b,h,w - 0000000 fbyte23[r/w] b,h,w 00000000 fbyte13[r/w] b,h,w 00000000 001590 h | 001ffc h - - - - reserved 002000 h ctrlr0[r/w] b,h,w -------- 000- 0001 statr0[r/w] b,h,w -------- 00000000 can 0 64msb 002004 h errcnt0 [r] b,h,w 00000000 00000000 btr0[r/w] b,h,w - 0100011 00000001 002008 h intr0[r] b,h,w 00000000 00000000 testr0[r/w] b,h,w -------- x00000 -- 00200c h brper0[r/w] b,h,w -------- ----0000 - 002010 h if1creq0[r/w] b,h,w 0 ------- 00000001 if1cmsk 0[r/w] b,h,w -------- 00000000 002014 h if1msk20[r/w] b,h,w 11- 11111 11111111 if1msk10[r/w] b,h,w 11111111 11111111 002018 h if1arb20[r/w] b,h,w 00000000 00000000 if1arb10[r/w] b,h,w 00000000 00000000 00201c h if1mctr0[r/w] b,h,w 00000000 0---0000 - 0 02020 h if1dta10[r/w] b,h,w 00000000 00000000 if1dta20[r/w] b,h,w 00000000 00000000 002024 h if1dtb10[r/w] b,h,w 00000000 00000000 if1dtb20[r/w] b,h,w 00000000 00000000
document number: 002- 0466 5 rev * a page 67 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 002028 h , 00202c h - - can 0 64msb 002030 h , 002034 h reserved (if1 data mirror) 002038 h , 00203c h - - 002040 h if2creq0[r/w] b,h,w 0 ------- 00000001 if2cmsk0[r/w] b,h,w -------- 00000000 002044 h if2msk20[r/w] b,h,w 11- 11111 11111111 if2msk10[r/w] b,h,w 11111111 11111111 002048 h if2arb20[r/w] b,h,w 00000000 00000000 if2arb10[r/w] b,h,w 00000000 00000000 00204c h if2mctr0[r/w] b,h,w 00000000 0---0000 - 002050 h if2dta10[r/w] b,h,w 00000000 00000000 if2dta20[r/w] b,h,w 00000000 00000000 002054 h if2dtb10[r/w] b,h,w 00000000 00000000 if2dtb20[r/w] b,h,w 00000000 00000000 002058 h , 00205c h - - 002060 h , 002064 h reserved (if2 data mirror) 002068 h | 00207c h - - 002080 h treqr20[r] b,h,w 00000000 00000000 treqr10[r] b,h,w 00000000 00000000 002084 h treqr40[r] b,h,w 00000000 00000000 treqr30[r] b,h,w 00000000 00000000 002088 h - - 00208c h - - 002090 h newdt20[r] b,h,w 00000000 00000000 newdt10[r] b,h,w 00000000 00000000 002094 h newdt40[r] b,h,w 00000000 00000000 newdt30[r] b,h,w 00000000 00000000 002098 h - - 00209c h - - 0020a0 h intpnd20[r] b,h,w 00000000 00000000 intpnd10[r] b ,h,w 00000000 00000000 0020a4 h intpnd40[r] b,h,w 00000000 00000000 intpnd30[r] b,h,w 00000000 00000000 0020a8 h - - 0020ac h - -
document number: 002- 0466 5 rev * a page 68 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 0020b0 h msgval20[r] b,h,w 00000000 00000000 msgval10[r] b,h,w 00000000 00000000 can 0 64msb 0020b4 h msgval40[r] b,h,w 00000000 00000000 msgval30[r] b,h,w 00000000 00000000 0020b8 h - - 0020bc h - - 0020c0 h | 0020fc h - - 002100 h ctrlr1[r/w] b,h,w -------- 000- 0001 statr1[r/w] b,h,w -------- 00000000 can 1 64msb 002104 h errcnt1 [r] b,h,w 00000000 00000000 btr1[r/w] b,h ,w - 0100011 00000001 002108 h intr1[r] b,h,w 00000000 00000000 testr1[r/w] b,h,w -------- x00000 -- 00210c h brper1[r/w] b,h,w -------- ----0000 - 002110 h if1creq1[r/w] b,h,w 0 ------- 00000001 if1cmsk1[r/w] b,h,w -------- 00000000 002114 h if1msk21[r/w ] b,h,w 11- 11111 11111111 if1msk11[r/w] b,h,w 11111111 11111111 002118 h if1arb21[r/w] b,h,w 00000000 00000000 if1arb11[r/w] b,h,w 00000000 00000000 00211c h if1mctr1[r/w] b,h,w 00000000 0---0000 - 002120 h if1dta11[r/w] b,h,w 00000000 00000000 if1dta21 [r/w] b,h,w 00000000 00000000 002124 h if1dtb11[r/w] b,h,w 00000000 00000000 if1dtb21[r/w] b,h,w 00000000 00000000 002128 h , 00212c h - - 002130 h , 002134 h reserved (if1 data mirror) 002138 h , 00213c h - - 002140 h if2creq1[r/w] b,h,w 0 ------- 00000001 if2cmsk1[r/w] b,h,w -------- 00000000 002144 h if2msk21[r/w] b,h,w 11- 11111 11111111 if2msk11[r/w] b,h,w 11111111 11111111 002148 h if2arb21[r/w] b,h,w 00000000 00000000 if2arb11[r/w] b,h,w 00000000 00000000 00214c h if2mctr1[r/w] b,h,w 00000000 0---0000 -
document number: 002- 0466 5 rev * a page 69 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 002150 h if2dta11[r/w] b,h,w 00000000 00000000 if2dta21[r/w] b,h,w 00000000 00000000 can 1 64msb 002154 h if2dtb11[r/w] b,h,w 00000000 00000000 if2dtb21[r/w] b,h,w 00000000 00000000 002158 h , 00215c h - - 002160 h , 002164 h reserved (if2 data mirror) 002168 h | 00217c h - - 002180 h treqr21[r] b,h,w 00000000 00000000 treqr11[r] b,h,w 00000000 00000000 002184 h treqr41[r] b,h,w 00000000 00000000 treqr31[r] b,h,w 00000000 00000000 002188 h - - 00218c h - - 002190 h newdt21[r] b,h,w 00000000 00000000 newdt11[r] b,h,w 00000000 00000000 002194 h newdt41[r] b,h,w 00000000 00000000 newdt31[r] b,h,w 00000000 00000000 002198 h - - 00219c h - - 0021a0 h intpnd21[r] b,h,w 00000000 00000000 intpnd11[r] b,h,w 00000000 00000000 0021a4 h intpnd41[r] b,h,w 0 0000000 00000000 intpnd31[r] b,h,w 00000000 00000000 0021a8 h - - 0021ac h - - 0021b0 h msgval21[r] b,h,w 00000000 00000000 msgval11[r] b,h,w 00000000 00000000 0021b4 h msgval41[r] b,h,w 00000000 00000000 msgval31[r] b,h,w 00000000 00000000 0021b8 h - - 0021bc h - - 0021c0 h | 0021fc h - - 002200 h | 0022fc h - - reserved
document number: 002- 0466 5 rev * a page 70 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 002300 h dfctlr[r/w] b,h,w - 0 ------ -------- - dfstr[r/w] b,h,w -----001 workflash 002304 h - - - - 002308 h flifctlr[r/w] b,h,w ---0 --00 - fliffer1[r/w] b,h,w -------- fliffer 2[r/w] b,h,w -------- 00230c h | 002ffc h - - - - reserved 003000 h seearx[r] b,h,w --000000 00000000 deearx[r] b,h,w --000000 00000000 xbs ram ecc control register 003004 h eecsrx[r/w] b,h,w ----00- 0 - efearx[r/w] b,h,w --000000 00000000 003008 h - efecr x[r/w] b,h,w ------- 0 00000000 00000000 00300c h tear0x[r] b,h,w 000----- -------- -- 000000 00000000 xbs ram diagnosis register 003010 h tear1x[r] b,h,w 000----- -------- -- 000000 00000000 003014 h tear2x[r] b,h,w 000----- -------- -- 000000 00000000 003018 h taearx[r/w] b,h,w --101111 11111111 tasarx[r/w] b,h,w --000000 00000000 00301c h tfecrx[r/w] b,h,w ----0000 ticrx[r/w] b,h,w ----0000 ttcrx[r/w] b,h,w ------ 00 00001100 003020 h tsrcrx[r/w] b,h,w 0 ------- - - tkccrx[r/w] b,h,w 00----00 003024 h se eara[r] b,h,w --000000 00000000 deeara[r] b,h,w --000000 00000000 backup ram ecc control register 003028 h eecsra[r/w] b,h,w ----00- 0 - efeara[r/w] b,h,w --000000 00000000 00302c h - efecra[r/w] b,h,w ------- 0 00000000 00000000
document number: 002- 0466 5 rev * a page 71 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 003030 h tear 0a[r] b,h,w 000----- -------- ----- 000 00000000 backup ram diagnosis register 003034 h tear1a[r] b,h,w 000----- -------- ----- 000 00000000 003038 h tear2a[r] b,h,w 000----- -------- ----- 000 00000000 00303c h taeara[r/w] b,h,w -----111 11111111 tasara[r/ w] b,h,w -----000 00000000 003040 h tfecra[r/w] b,h,w ----0000 ticra[r/w] b,h,w ----0000 ttcra[r/w] b,h,w ------ 00 00001100 003044 h tsrcra[r/w] b,h,w 0 ------- - - tkccra[r/w] b,h,w 00----00 003048 h | 0030fc h - - - - reserved 003100 h busdigsr0[r/w] h, w 00000000 0-----00 busdigsr1[r/w] h,w 00000000 0-----00 bus diagnosis 003104 h busdigsr2[r/w] h,w 00000000 0-----00 buststr0[r/w] h,w 00--0000 00000000 003108 h busadr0[r] w 00000000 00000000 00000000 00000000 00310c h busadr1[r] w 00000000 00000000 000 00000 00000000 003110 h busadr2[r] w 00000000 00000000 00000000 00000000 003114 h - busdigsr3[r/w] h,w 00000000 0-----00 003118 h busdigsr4[r/w] h,w 00000000 0-----00 buststr1[r/w] h,w 00--0000 00000000 00311c h - 003120 h busadr3[r] w 00000000 000000 00 00000000 00000000 003124 h busadr4[r] w 00000000 00000000 00000000 00000000 bus diagnosis 003128 h | 003ffc h - - - - reserved 004000 h | 005ffc h backup ram backup ram area 006000 h | 00cffc h - - - - reserved
document number: 002- 0466 5 rev * a page 72 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d000 h cif0[r] w 00000100 11111111 0101101 1 11111111 flexray cif *5 00d004 h cif1[r/w] w 00000000 ------- 0 - 0000000 -------- 00d008 h | 00d00c h - - - - reserved 00d010 h - flexray gif *5 00d014 h - 00d018 h - - - - 00d01c h lck[r/w] w -------- -------- -------- 00000000 00d020 h eir[r/w] w -----000 ----- 000 ---- 0000 00000000 flexray int *5 00d024 h sir[r/w] w ------00 ------ 00 00000000 00000000 00d028 h eils[r/w] w -----000 ----- 000 ---- 0000 00000000 00d02c h sils[r/w] w ------11 ------ 11 11111111 11111111 00d030 h eies[r/w] w -----000 ----- 000 ---- 0000 00000000 00d034 h eier[r/w] w -----000 ----- 000 ---- 0000 00000000 00d038 h sies[r/w] w ------00 ------ 00 00000000 00000000 00d03c h sier[r/w] w ------00 ------ 00 00000000 00000000 00d040 h ile[r/w] w -------- -------- -------- ------ 00 0 0d044 h t0c[r/w] w --000000 00000000 - 0000000 ------ 00 00d048 h t1c[r/w] w --000000 00000010 -------- ------ 00 00d04c h stpw1[r/w] w --000000 00000000 --000000 - 0000000 00d050 h stpw2[r] w -----000 00000000 ----- 000 00000000 00d054 h | 00d07c h - - - - r eserved
document number: 002- 0466 5 rev * a page 73 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d080 h succ1[r/w] w ----1100 01000000 00010- 00 1 --- 0000 flexray suc *5 00d084 h succ2[r/w] w ----0001 --- 00000 00000101 00000100 00d088 h succ3[r/w] w -------- -------- -------- 00010001 00d08c h nemc[r/w] w -------- -------- -------- ---- 0000 flexray nem *5 00d090 h prtc1[r/w] w 000010- 0 01001100 0000- 110 00110011 flexray prt *5 00d094 h prtc2[r/w] w --001111 00101101 --001010 -- 001110 00d098 h mhdc[r/w] w ---00000 00000000 -------- - 0000000 flexray mhd *5 00d09c h - reserved 00d0a0 h g tuc1[r/w] w -------- ---- 0000 00000010 10000000 flexray gtu *5 00d0a4 h gtuc2[r/w] w -------- ----0010 -- 000000 00001010 00d0a8 h gtuc3[r/w] w - 0000010 - 0000010 00000000 00000000 00d0ac h gtuc4[r/w] w --000000 00001000 -- 000000 00000111 00d0b0 h gtuc5[r /w] w 00001110 --- 00000 00000000 00000000 00d0b4 h gtuc6[r/w] w -----000 00000010 ----- 000 00000000 00d0b8 h gtuc7[r/w] w ------ 00 00000010 ------ 00 00000100 00d0bc h gtuc8[r/w] w ---00000 00000000 -------- -- 000010 00d0c0 h gtuc9[r/w] w -------- ------ 00 ---00001 --000001 00d0c4 h gtuc10[r/w] w -----000 00000010 -- 000000 00000101 00d0c8 h gtuc11[r/w] w -----000 ----- 000 ------ 00 ------ 00 00d0cc h | 00d0fc h - reserved
document number: 002- 0466 5 rev * a page 74 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d100 h ccsv[r] w --000000 00010000 - 100-- 00 00000000 flexray suc *5 00d104 h ccev[r] w -------- -------- ---00000 00-- 0000 00d108 h 00d10c h - reserved 00d110 h scv[r] w -----000 00000000 ----- 000 00000000 flexray gtu *5 00d114 h mtccv[r] w -------- --000000 -- 000000 00000000 00d118 h rcv[r] w -------- -------- ---- 0000 00000000 00d11c h ocv[r] w -------- ----- 000 00000000 00000000 00d120 h sfs[r] w -------- ---- 0000 00000000 00000000 flexray gtu *5 00d124 h swnit[r] w -------- -------- ---- 0000 00000000 00d128 h acs[r/w] w -------- -------- ---00000 --- 00000 00d12c h - 00d1 30 h esid1[r] w -------- -------- 00---- 00 00000000 00d134 h esid2[r] w -------- -------- 00---- 00 00000000 00d138 h esid3[r] w -------- -------- 00---- 00 00000000 00d13c h esid4[r] w -------- -------- 00---- 00 00000000 00d140 h esid5[r] w -------- ---- ---- 00---- 00 00000000 00d144 h esid6[r] w -------- -------- 00---- 00 00000000 00d148 h esid7[r] w -------- -------- 00---- 00 00000000 00d14c h esid8[r] w -------- -------- 00---- 00 00000000 00d150 h esid9[r] w -------- -------- 00---- 00 00000000 00d 154 h esid10[r] w -------- -------- 00---- 00 00000000 00d158 h esid11[r] w -------- -------- 00---- 00 00000000
document number: 002- 0466 5 rev * a page 75 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d15c h esid12[r] w -------- -------- 00---- 00 00000000 flexray gtu *5 00d160 h esid13[r] w -------- -------- 00---- 00 00000000 00d164 h esid1 4[r] w -------- -------- 00---- 00 00000000 00d168 h esid15[r] w -------- -------- 00---- 00 00000000 00d16c h - 00d170 h osid1[r] w -------- -------- 00---- 00 00000000 00d174 h osid2[r] w -------- -------- 00---- 00 00000000 00d178 h osid3[r] w -------- -------- 00---- 00 00000000 00d17c h osid4[r] w -------- -------- 00---- 00 00000000 00d180 h osid5[r] w -------- -------- 00---- 00 00000000 00d184 h osid6[r] w -------- -------- 00---- 00 00000000 00d188 h osid7[r] w -------- -------- 00---- 00 00000000 00d18c h osid8[r] w -------- -------- 00---- 00 00000000 00d190 h osid9[r] w -------- -------- 00---- 00 00000000 00d194 h osid10[r] w -------- -------- 00---- 00 00000000 00d198 h osid11[r] w -------- -------- 00---- 00 00000000 00d19c h osid12[r] w ---- ---- -------- 00---- 00 00000000 00d1a0 h osid13[r] w -------- -------- 00---- 00 00000000 00d1a4 h osid14[r] w -------- -------- 00---- 00 00000000 00d1a8 h osid15[r] w -------- -------- 00---- 00 00000000 00d1ac h - reserved
document number: 002- 0466 5 rev * a page 76 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d1b0 h nmv1[r] w 00000 000 00000000 00000000 00000000 flexray nem *5 00d1b4 h nmv2[r] w 00000000 00000000 00000000 00000000 00d1b8 h nmv3[r] w 00000000 00000000 00000000 00000000 00d1bc h | 00d2fc h - reserved 00d300 h mrc[r/w] w ----- 001 10000000 00000000 00000000 flexray mhd *5 00d304 h frf[r/w] w ------- 1 10000000 --- 00000 00000000 00d308 h frfm[r/w] w -------- -------- ---00000 000000-- 00d30c h fcl[r/w] w -------- -------- -------- 10000000 00d310 h mhds[r/w] w - 0000000 - 0000000 - 0000000 0 0000000 00d314 h ldts[r] w ----- 000 00000000 ----- 000 00000000 00d318 h fsr[r] w -------- -------- 00000000 ----- 000 00d31c h mhdf[r/w] w -------- -------- ------- 0 00000000 00d320 h txrq1[r] w 00000000 00000000 00000000 00000000 00d324 h txrq2[r] w 00000000 00000000 00000000 000000 00 00d328 h txrq3[r] w 00000000 00000000 00000000 00000000 00d32c h txrq4[r] w 00000000 00000000 00000000 00000000 00d330 h ndat1[r] w 00000000 00000000 00000000 00000000 00d334 h ndat2[r] w 00000000 00000000 00000000 00000000 00d338 h ndat3[r] w 0000 0000 00000000 00000000 00000000
document number: 002- 0466 5 rev * a page 77 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d33c h ndat4[r] w 00000000 00000000 00000000 00000000 flexray mhd *5 00d340 h mbsc1[r] w 00000000 00000000 00000000 00000000 00d344 h mbsc2[r] w 00000000 00000000 00000000 00000000 00d348 h mbsc3[r] w 00000000 000 00000 00000000 00000000 00d34c h mbsc4[r] w 00000000 00000000 00000000 00000000 00d350 h | 00d3ec h - reserved 00d3f0 h crel[r] w 00010000 00111001 00000010 00000110 flexray gif *5 00d3f4 h endn[r] w 10000111 01100101 01000011 00100001 00d3f8 h | 00d3fc h - reserved 00d400 h | 00d4fc h wrdsn[1 - 64][r/w] w 00000000 00000000 00000000 00000000 flexray ibf *5 00d500 h wrhs1[r/w] w --000000 - 0000000 ----- 000 00000000 00d504 h wrhs2[r/w] w -------- - 0000000 ----- 000 00000000 00d508 h wrhs3[r/w] w -------- ------ -- ----- 000 00000000 00d50c h - 00d510 h ibcm[r/w] w -------- ------ 00 -------- -----000 00d514 h ibcr[r/w] w 0 ------- - 0000000 0 ------- - 0000000 00d518 h | 00d5fc h - reserved
document number: 002- 0466 5 rev * a page 78 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 + 3 00d600 h | 00d6fc h rddsn[1 - 64][r] w 00000000 00000000 00000000 000000 00 flexray obf *5 00d700 h rdhs1[r] w --000000 - 0000000 ----- 000 00000000 00d704 h rdhs2[r] w - 0000000 - 0000000 ----- 000 00000000 00d708 h rdhs3[r] w --000000 --000000 ----- 000 00000000 00d70c h mbs[r] w --000000 --000000 00- 00000 00000000 00d710 h obc m[r/w] w -------- ------ 00 -------- ------00 00d714 h obcr[r/w] w -------- - 0000000 0 -----00 - 0000000 00d718 h | 00d7fc h - reserved 00d800 h | 00effc h - reserved 00f000 h | 00fefc h - reserved [s] 00ff00 h dsucr[r/w] b,h,w -------- ------- 0 - - ocdu [s] 00ff04 h | 00ff0c h - - - - reserved [s] 00ff10 h pcsr[r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00ff14 h pssr[r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00ff18 h | 00fff4 h - - - - reserved [s] 00fff8 h edir1[r] b,h,w xxxxxxxx xxxxxxxx xxx xxxxx xxxxxxxx ocdu [s] 00fffc h edir0[r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx [s]: it is a system register. the illegal instruction exception (data access error) is generated when reading and writing to these registers in the user mode. *5: for fle xray, the mb91f583 a mg/f584 a mg/f585a mg/f583 a mj/f584a mj/f585a mj has corresponding functions.
document number: 002- 0466 5 rev * a page 79 of 175 mb91580m/s series the following registers are reserved registers for models without the flexray function. 000125 h irpr2l[5:4], 000e68 h , 0004e8 h - 0004ef h , 00d000 h - 00d717 h
document number: 002- 0466 5 rev * a page 80 of 175 mb91580m/s series ? i/o map (mb 91f583 a s/f584 a s/f585 as) address address offset value/register name block +0 +1 +2 +3 000000 h - pdr01[r/w] b,h,w xxxxxxxx pdr02[r/w] b,h,w xxxxxxxx pdr03[r/w] b,h,w xxxxxxxx port data register 000004 h pdr04[r/w] b,h,w xxxxxxxx pdr05[r/w] b,h,w - xxxxxxx - pdr07[r/w] b,h,w ----- xxx 000008 h - pdr09[r/w] b,h,w --- xx--- - - 00000c h - - - - 000010 h | 000038 h - - - - reserved 00003c h wdtcr0[r/w] b,h,w - 0 --0000 wdtcpr0[w] b,h,w 00000000 wdtcr1[r] b,h,w ----0010 wdtcpr1[w] b,h,w 00000000 watchdog timer [s ] 000040 h - - - reserved 000044 h dicr[r/w] b -------0 - - - delay interrupt 000048 h | 00005c h - - reserved 000060 h tmrlra0[r/w] h xxxxxxxx xxxxxxxx tmr0[r] h xxxxxxxx xxxxxxxx reload timer 0 000064 h tmrlrb0[r/w] h xxxxxxxx xxxxxxxx tmcsr0[r/w] b,h,w 0 0000000 0- 000000 000068 h | 00007c h - - - - reserved 000080 h bt0tmr[r] h 00000000 00000000 bt0tmcr[r/w] h - 0000000 00000000 base timer 0 000084 h bt0tmcr2 [r/w] b -------0 bt0stc [r/w] b - 0 - 0 - 0 - 0 - - 000088 h bt0pcsr/bt0prll [r/w] h 00000000 00000000 bt 0pdut/bt0prlh/bt0dtbf [r/w] h 00000000 00000000 00008c h - - - -
document number: 002- 0466 5 rev * a page 81 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000090 h bt1tmr[r] h 00000000 00000000 bt1tmcr[r/w] h - 0000000 00000000 base timer 1 000094 h bt1tmcr2 [r/w] b -------0 bt1stc [r/w] b - 0 - 0 - 0 - 0 - - 000098 h bt1pcsr/bt1prll [r/ w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf [r/w] h 00000000 00000000 00009c h btsel01[r/w] b ----0000 - btsssr[w] b,h -------- ------11 base timer 0, 1 0000a0 h | 0000fc h - - - - reserved 000100 h tmrlra1[r/w] h xxxxxxxx xxxxxxxx tmr1[r] h xxxxxxxx xx xxxxxx reload timer 1 000104 h tmrlrb1[r/w] h xxxxxxxx xxxxxxxx tmcsr1[r/w] b,h,w 00000000 0- 000000 000108 h tmrlra2[r/w] h xxxxxxxx xxxxxxxx tmr2[r] h xxxxxxxx xxxxxxxx reload timer 2 00010c h tmrlrb2[r/w] h xxxxxxxx xxxxxxxx tmcsr2[r/w] b,h,w 00000000 0- 000000 000110 h tmrlra3[r/w] h xxxxxxxx xxxxxxxx tmr3[r] h xxxxxxxx xxxxxxxx reload timer 3 000114 h tmrlrb3[r/w] h xxxxxxxx xxxxxxxx tmcsr3[r/w] b,h,w 00000000 0- 000000 000118 h | 00011c h - - - - reserved
document number: 002- 0466 5 rev * a page 82 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000120 h irpr0h[r] b,h,w 00------ irpr0l[r] b,h,w 00------ irpr1h[r] b,h,w 00------ irpr1l[r] b,h,w -------- interrupt request batch read register 000124 h irpr2h[r] b,h,w -------- irpr2l[r] b,h,w * 5 0000---- irpr3h[r] b,h,w 00------ irpr3l[r] b,h,w 00------ 000128 h irpr4h[r] b,h, w 00------ irpr4l[r] b,h,w 000000-- irpr5h[r] b,h,w 00------ irpr5l[r] b,h,w 00------ 00012c h irpr6h[r] b,h,w 0000---- irpr6l[r] b,h,w 00------ irpr7h[r] b,h,w 00------ irpr7l[r] b,h,w -------- 000130 h irpr8h[r] b,h,w -------- irpr8l[r] b,h,w 00------ irpr9h[r] b,h,w 00------ irpr9l[r] b,h,w 00------ 000134 h irpr10h[r] b,h,w 00------ irpr10l[r] b,h,w 00------ irpr11h[r] b,h,w 00------ irpr11l[r] b,h,w 0000000- 000138 h irpr12h[r] b,h,w 0000000- irpr12l[r] b,h,w 00000000 irpr13h[r] b,h,w 0000000- irpr 13l[r] b,h,w ---00--- 00013c h irpr14h[r] b,h,w 00------ irpr14l[r] b,h,w 00------ irpr15h[r] b,h,w 00000000 irpr15l[r] b,h,w 0000---- 000140 h irpr16h[r] b,h,w 00------ irpr16l[r] b,h,w -------- irpr17h[r] b,h,w -------- irpr17l[r] b,h,w -------- 000144 h irpr18h[r]b,h,w -------- irpr18l[r]b,h,w 000000-- - - 000148 h | 0001fc h - - - - reserved 000200 h pcn0[r/w] b,h,w 00000000 000000- 0 pcsr0[w] h,w xxxxxxxx xxxxxxxx ppg0 000204 h pdut0[w] h,w xxxxxxxx xxxxxxxx ptmr0[r] h,w 11111111 11111111 000208 h pcn1[r/w] b,h,w 00000000 000000- 0 pcsr1[w] h,w xxxxxxxx xxxxxxxx ppg1 00020c h pdut1[w] h,w xxxxxxxx xxxxxxxx ptmr1[r] h,w 11111111 11111111 000210 h pcn2[r/w] b,h,w 00000000 000000- 0 pcsr2[w] h,w xxxxxxxx xxxxxxxx ppg2 000214 h pdut2[w] h,w xxxxxxxx xxx xxxxx ptmr2[r] h,w 11111111 11111111 000218 h pcn3[r/w] b,h,w 00000000 000000- 0 pcsr3[w] h,w xxxxxxxx xxxxxxxx ppg3 00021c h pdut3[w] h,w xxxxxxxx xxxxxxxx ptmr3[r] h,w 11111111 11111111
document number: 002- 0466 5 rev * a page 83 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000220 h pcn4[r/w] b,h,w 00000000 000000- 0 pcsr4[w] h,w xxxxxx xx xxxxxxxx ppg4 000224 h pdut4[w] h,w xxxxxxxx xxxxxxxx ptmr4[r] h,w 11111111 11111111 000228 h pcn5[r/w] b,h,w 00000000 000000- 0 pcsr5[w] h,w xxxxxxxx xxxxxxxx ppg5 00022c h pdut5[w] h,w xxxxxxxx xxxxxxxx ptmr5[r] h,w 11111111 11111111 000230 h | 0002b c h - - reserved 0002c0 h gtrs0[r/w] b,h,w - 0000000 - 0000000 gtrs1[r/w] b,h,w - 0000000 - 0000000 ppg control 0002c4 h gtrs2[r/w] b,h,w - 0000000 - 0000000 - 0002c8 h - - 0002cc h - - 0002d0 h - - 0002d4 h - - 0002d8 h gtren0[r/w] h,w -------- --000000 - 0002dc h - - reserved 0002e0 h - gatec0[r/w] b,h,w ------00 - gatec2[r/w] b,h,w ------00 ppg gate control 0002e4 h - gatec4[r/w] b,h,w ------00 - - 0002e8 h - - - - 0002ec h - - - - reserved 0002f0 h rcrh0[w] h,w 00000000 rcrl0[w] b,h,w 00000000 udcrh0 [r] h,w 00000000 udcrl0[r] b,h,w 00000000 u/d counter 0 0002f4 h ccr0[r/w] b,h 00000000 - 0001000 - csr0[r] b 00000000 0002f8 h rcrh1[w] h,w 00000000 rcrl1[w] b,h,w 00000000 udcrh1[r] h,w 00000000 udcrl1[r] b,h,w 00000000 u/d counter 1 0002fc h ccr1[r/ w] b,h 00000000 - 0001000 - csr1[r] b 00000000 000300 h - reserved 000304 h - - - - reserved 000308 h - reserved 00030c h - - - -
document number: 002- 0466 5 rev * a page 84 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000310 h - - mpucr[r/w] h 000000- 0 ----0100 mpu [s] (only the cpu can access this area) 000314 h - - - - 000318 h - 00031c h - - - 000320 h dpvar[r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000324 h - - dpvsr[r/w] h -------- 00000--0 000328 h dear[r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00032c h - - desr[r/w] h -------- 00000--0 000330 h pabr0[r/w] w xxxxxxxx xxxxxxxx xxxxx xxx xxxx0000 000334 h - - pacr0[r/w] h 000000- 0 00000--0 000338 h pabr1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00033c h - - pacr1[r/w] h 000000- 0 00000--0 000340 h pabr2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000344 h - - pacr2[r/w] h 000000- 0 00000--0 000348 h pabr3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00034c h - - pacr3[r/w] h 000000- 0 00000--0 000350 h pabr4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000354 h - - pacr4[r/w] h 000000- 0 00000--0 000358 h pabr5[r/w] w xxxxxxxx xxxxxx xx xxxxxxxx xxxx0000 00035c h - - pacr5[r/w] h 000000- 0 00000--0 000360 h pabr6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000364 h - - pacr6[r/w] h 000000- 0 00000--0
document number: 002- 0466 5 rev * a page 85 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000368 h pabr7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 mpu [s] (only the cpu can access this area) 00036c h - - pacr7[r/w] h 000000- 0 00000--0 000370 h - reserved [s] 000374 h - - - 000378 h - 00037c h - - - 000380 h - 000384 h - - - 000388 h - 00038c h - - - 000390 h - 000394 h - - - reserved [s] 000398 h - 00039c h - - - 0003a0 h - 0003a4 h - - - 0003a8 h - 0003ac h - - - 0003b0 h | 0003cc h - - - - reserved [s] 0003d0 h - reserved [s] 0003d4 h - 0003d8 h - 0003dc h - 0003e0 h | 0003fc h - - - - reserved [s]
document number: 002- 0466 5 rev * a page 86 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000400 h icsel0[r/w] b,h,w -----000 icse l1[r/w] b,h,w -------0 icsel2[r/w] b,h,w -------0 icsel3[r/w] b,h,w -------0 generation and clear of dma transfer request 000404 h icsel4[r/w] b,h,w -------0 icsel5[r/w] b,h,w -------0 icsel6[r/w] b,h,w -------0 icsel7[r/w] b,h,w -----000 000408 h icsel8[ r/w] b,h,w -------0 icsel9[r/w] b,h,w -------0 icsel10[r/w] b,h,w ------00 icsel11[r/w] b,h,w -------0 00040c h icsel12[r/w] b,h,w -------0 icsel13[r/w] b,h,w -------0 icsel14[r/w] b,h,w -------0 icsel15[r/w] b,h,w -------0 000410 h icsel16[r/w] b,h,w -------0 icsel17[r/w] b,h,w -------0 icsel18[r/w] b,h,w -------0 icsel19[r/w] b,h,w -------0 000414 h icsel20[r/w] b,h,w -------0 icsel21[r/w] b,h,w -----000 icsel22[r/w] b,h,w -----000 icsel23[r/w] b,h,w -----000 000418 h icsel24[r/w] b,h,w -----000 icsel 25[r/w] b,h,w -----000 icsel26[r/w] b,h,w -------0 icsel27[r/w] b,h,w -------0 00041c h - - - - 000420 h - - - - 000424 h | 00043c h - - - - reserved 000440 h icr00[r/w] b,h,w ---11111 icr01[r/w] b,h,w ---11111 icr02[r/w] b,h,w ---11111 icr03[r/w] b,h,w ---11111 interrupt controller [s] 000444 h icr04[r/w] b,h,w ---11111 icr05[r/w] b,h,w ---11111 icr06[r/w] b,h,w ---11111 icr07[r/w] b,h,w ---11111 000448 h icr08[r/w] b,h,w ---11111 icr09[r/w] b,h,w ---11111 icr10[r/w] b,h,w ---11111 icr11[r/w] b,h,w ---1 1111 00044c h icr12[r/w] b,h,w ---11111 icr13[r/w] b,h,w ---11111 icr14[r/w] b,h,w ---11111 icr15[r/w] b,h,w ---11111 000450 h icr16[r/w] b,h,w ---11111 icr17[r/w] b,h,w ---11111 icr18[r/w] b,h,w ---11111 icr19[r/w] b,h,w ---11111 000454 h icr20[r/w] b, h,w ---11111 icr21[r/w] b,h,w ---11111 icr22[r/w] b,h,w ---11111 icr23[r/w] b,h,w ---11111 000458 h icr24[r/w] b,h,w ---11111 icr25[r/w] b,h,w ---11111 icr26[r/w] b,h,w ---11111 icr27[r/w] b,h,w ---11111 00045c h icr28[r/w] b,h,w ---11111 icr29[r/w] b,h, w ---11111 icr30[r/w] b,h,w ---11111 icr31[r/w] b,h,w ---11111 000460 h icr32[r/w] b,h,w ---11111 icr33[r/w] b,h,w ---11111 icr34[r/w] b,h,w ---11111 icr35[r/w] b,h,w ---11111 000464 h icr36[r/w] b,h,w ---11111 icr37[r/w] b,h,w ---11111 icr38[r/w] b,h,w ---11111 icr39[r/w] b,h,w ---11111 000468 h icr40[r/w] b,h,w ---11111 icr41[r/w] b,h,w ---11111 icr42[r/w] b,h,w ---11111 icr43[r/w] b,h,w ---11111 00046c h icr44[r/w] b,h,w ---11111 icr45[r/w] b,h,w ---11111 icr46[r/w] b,h,w ---11111 icr47[r/w] b,h,w --- 11111
document number: 002- 0466 5 rev * a page 87 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000470 h | 00047c h - - - - reserved [s] 000480 h rstrr[r] b,h,w xxxx -- xx rstcr[r/w] b,h,w 111----0 stbcr[r/w] b,h,w 000---11 * - reset control [s] power consumption control [s] * writing to stbcr by dma is disabled. 000484 h - - - - reserved [s] 000488 h divr0[r/w] b,h,w 000----- - divr2[r/w] b,h,w 0011---- - clock control [s] 00048c h - - - - reserved [s] 000490 h iorr0[r/w] b,h,w - 0000000 iorr1[r/w] b,h,w - 0000000 iorr2[r/w] b,h,w - 0000000 iorr3[r/w] b,h,w - 0000000 dma transfer request from a per ipheral [s] 000494 h iorr4[r/w] b,h,w - 0000000 iorr5[r/w] b,h,w - 0000000 iorr6[r/w] b,h,w - 0000000 iorr7[r/w] b,h,w - 0000000 000498 h - - - - 00049c h - - - - 0004a0 h - - - - reserved 0004a4 h canpre[r/w] b,h,w ---00000 - - - can prescaler 0004a8 h | 0 004ac h - - - - reserved 0004b0 h - - - - reserved 0004b4 h | 0004c0 h - - - - reserved 0004c4 h cucr1[r/w] b,h,w -------- ---0 --00 cutd1[r/w] b,h,w 11000011 01010000 wdt1 calibration 0004c8 h cutr1[r] b,h,w -------- 00000000 00000000 00000000 0004cc h | 00 04dc h - - - - reserved 0004e0 h - - cscfg[r/w] b,h,w ---0 ---- cmcfg[r/w] b,h,w 00000000 clock monitor 0004e4 h - - - -
document number: 002- 0466 5 rev * a page 88 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 0004e8 h pll2divm[r/w] b,h,w ----0000 pll2divn[r/w] b,h,w - 0000000 pll2divg[r/w] b,h,w ----0000 pll2mulg[r/w] b,h,w 00000000 fl exray clock control *5 0004ec h pll2ctrl[r/w] b,h,w ----0000 pll2divk[r/w] b,h,w -------0 clkr2[r/w] b,h,w 000--000 - 0004f0 h | 0004fc h - - - - reserved 000500 h - reserved 000504 h - reserved 000508 h | 00050c h - - - - reserved 000510 h cselr[r/w] b,h,w - 0 ----00 cmonr[r] b,h,w - 01---00 mtmcr[r/w] b,h,w 00001111 - clock control [s] 000514 h pllcr[r/w] b,h,w 00- 00000 11110000 cstbr[r/w] b,h,w ----0000 ptmcr[r/w] b,h,w 00------ 000518 h - - cpuar[r/w] b,h,w 0 --- xxxx - reset [s] 00051c h - - - reserved [s] 000520 h ccpsselr[r/w] b,h,w -------0 - - ccpsdivr[r/w] b,h,w - 000- 000 clock control 2 000524 h - ccpllfbr[r/w] b,h,w - 0000000 ccssfbr0[r/w] b,h,w --000000 ccssfbr1[r/w] b,h,w ---00000 000528 h - ccssccr0[r/w] b,h,w ----0000 ccssccr1[r/w] b,h,w 000----- - ------- 00052c h - cccgrcr0[r/w] b,h,w 00----00 cccgrcr1[r/w] b,h,w 00000000 cccgrcr2[r/w] b,h,w 00000000 000530 h - - ccpmucr0[r/w] b,h,w 0 -----00 ccpmucr1[r/w] b,h,w 0 --00000 000534 h - - - - 000538 h - - - - 00053c h - - - - 000540 h | 00054c h - - - - reserved 000550 h eirr0[r/w] b,h,w - xxxxxxx enir0[r/w] b,h,w - 0000000 elvr0[r/w] b,h,w --000000 00000000 external interrupt (int0 to 6)
document number: 002- 0466 5 rev * a page 89 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000554 h | 000568 h - - - - reserved 00056c h - csvcr[r/w] b - 0 --1 --0 - - csv 000570 h crtr[r/w] b,h,w 01111111 - - - wdt1 calibration (trimming) 000574 h | 00057c h - - - - reserved 000580 h regsel[r/w] b,h,w 01--110- - - - regulator control 000584 h lvd5r[r/w] b,h,w -------1 lvd5f[r/w] b,h,w 001100- 1 lvd[r/w] b,h,w 01000--0 - low - voltage detection 000588 h | 00058c h - - - - reserved 000590 h pmustr [r/w] b,h,w 0 -----1x pmuctlr[r/w] b,h,w 0 - 00---- pwrtmctl[r/w] b,h,w -----011 - pmu 000594 h - pmuintf1[r/w] b,h,w 00000000 pmuintf2[r/w] b,h,w - 00----- - 000598 h - - - - 00059c h - - - - 0005a0 h | 0005fc h - - - - reser ved 000600 h | 00060c h - reserved [s] 000610 h | 00063c h - - - - reserved [s] 000640 h | 00064c h - reserved [s] 000650 h | 00067c h - - - - reserved [s] 000680 h | 00068c h - reserved [s]
document number: 002- 0466 5 rev * a page 90 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000690 h | 0006bc h - - - - reserved [s] 0006c0 h | 0006cc h - reserved [s] 0006d0 h | 0006f0 h - - - - reserved 0006f4 h - reserved 0006f8 h | 0006fc h - - - - reserved 000700 h - reserved 000704 h | 00070c h - - - - reserved 000710 h bpccra[r/w] b 00000000 bpccrb[r/w] b 00000000 bpccrc[r/w] b 00000000 - bus performance counter 000714 h bpctra[r/w] w 00000000 00000000 00000000 00000000 000718 h bpctrb[r/w] w 00000000 00000000 00000000 00000000 00071c h bpctrc[r/w] w 00000000 00000000 00000000 00000000 000720 h | 0007f8 h - - - - reserved 0007fc h bmodr[r] b,h,w xxxxxxxx - - - o peration mode 000800 h | 00083c h - - - - reserved [s] 000840 h fctlr[r/w] h - 0 -- 1000 0--0 ---- - fstr[r/w] b -----001 flash memory register [s] 000844 h - - - - reserved [s] 000848 h | 000854 h - - - - reserved [s] 000858 h - - wren[r/w] h 00000000 00000000 wild register [s]
document number: 002- 0466 5 rev * a page 91 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00085c h | 00087c h - - - - reserved [s] 000880 h wrar00[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 000884 h wrdr00[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000888 h wrar01[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00088c h wrdr01[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000890 h wrar02[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 000894 h wrdr02[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000898 h wrar03[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00089c h wrdr03[r /w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a0 h wrar04[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008a4 h wrdr04[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a8 h wrar05[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ac h wrdr05[r/w] w xxxxxxxx x xxxxxxx xxxxxxxx xxxxxxxx 0008b0 h wrar06[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008b4 h wrdr06[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b8 h wrar07[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008bc h wrdr07[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c0 h wrar08[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008c4 h wrdr08[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c8 h wrar09[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008cc h wrdr09[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
document number: 002- 0466 5 rev * a page 92 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 0008d0 h wrar10[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 0008d4 h wrdr10[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d8 h wrar11[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008dc h wrdr11[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000 8e0 h wrar12[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008e4 h wrdr12[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e8 h wrar13[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ec h wrdr13[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f0 h wrar14[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008f4 h wrdr14[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f8 h wrar15[r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008fc h wrdr15[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000900 h | 000bf8 h - - - - reserved 000bfc h - uer[w] b,h,w -------- ------- x ocdu
document number: 002- 0466 5 rev * a page 93 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000c00 h dccr0[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 dma controller [s] 000c04 h dcsr0[r/w] h 0 ------- ----- 000 dtcr0[r/w] h 00000000 00000000 000c08 h dsar0[r/w] w xxxxxxxx xxxxxxxx xxx xxxxx xxxxxxxx 000c0c h ddar0[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c10 h dccr1[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c14 h dcsr1[r/w] h 0 ------- ----- 000 dtcr1[r/w] h 00000000 00000000 000c18 h dsar1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx x xxxxxxx 000c1c h ddar1[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c20 h dccr2[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c24 h dcsr2[r/w] h 0 ------- ----- 000 dtcr2[r/w] h 00000000 00000000 000c28 h dsar2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c2c h ddar2[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c30 h dccr3[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c34 h dcsr3[r/w] h 0 ------- ----- 000 dtcr3[r/w] h 00000000 00000000 000c38 h dsar3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c 3c h ddar3[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c40 h dccr4[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c44 h dcsr4[r/w] h 0 ------- ----- 000 dtcr4[r/w] h 00000000 00000000
document number: 002- 0466 5 rev * a page 94 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000c48 h dsar4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dma controller [s] 000c4c h ddar4[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c50 h dccr5[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c54 h dcsr5[r/w] h 0 ------- ----- 000 dtcr5[r/w] h 00000000 00000000 000c58 h dsar5[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx x xxxxxxx 000c5c h ddar5[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c60 h dccr6[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c64 h dcsr6[r/w] h 0 ------- ----- 000 dtcr6[r/w] h 00000000 00000000 000c68 h dsar6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c6c h ddar6[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c70 h dccr7[r/w] w 0 ----000 --00-- 00 00000000 0 - 000000 000c74 h dcsr7[r/w] h 0 ------- ----- 000 dtcr7[r/w] h 00000000 00000000 000c78 h dsar7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c 7c h ddar7[r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c80 h | 000df0 h - - - - 000df4 h - - dnmir[r/w] b 0 ------0 dilvr[r/w] b ---11111 000df8 h dmacr[r/w] w 0 ------- -------- 0 ------- -------- 000dfc h - - - - reserved [s] 000e00 h - ddr01[r/w] b,h 0 0000000 ddr02[r/w] b,h 00000000 ddr03[r/w] b,h 00000000 data direction register 000e04 h ddr04[r/w] b,h 00000000 ddr05[r/w] b,h - 0000000 - ddr07[r/w] b,h -----000 000e08 h - ddr09[r/w] b,h ---00--- - - 000e0c h - - - -
document number: 002- 0466 5 rev * a page 95 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000e10 h | 000e1c h - - - - reserve d 000e20 h - pfr01[r/w] b,h 00000000 pfr02[r/w] b,h 00000000 pfr03[r/w] b,h 00000000 port function register 000e24 h pfr04[r/w] b,h 00000000 pfr05[r/w] b,h - 0000000 - pfr07[r/w] b,h -----000 000e28 h - pfr09[r/w] b,h ---00--- - - 000e2c h - - - - 000e3 0 h | 000e3c h - - - - reserved 000e40 h - pddr01[r] b,h,w xxxxxxxx pddr02[r] b,h,w xxxxxxxx pddr03[r] b,h,w xxxxxxxx input data direct read register 000e44 h pddr04[r] b,h,w xxxxxxxx pddr05[r] b,h,w - xxxxxxx - pddr07[r] b,h,w ----- xxx 000e48 h - pddr09[r] b,h,w --- xx--- - - 000e4c h - - - - 000e50 h | 000e5c h - - - - reserved 000e60 h epfr00[r/w] b,h -------0 epfr01[r/w] b,h ------00 epfr02[r/w] b,h -----000 epfr03[r/w] b,h --000000 extended port function register 000e64 h - - epfr06[r/w] b,h ------00 ep fr07[r/w] b,h ----0000 000e68 h epfr08[r/w] b,h *5 ----0000 epfr09[r/w] b,h -------0 epfr10[r/w] b,h - 0000000 - 000e6c h - - - - 000e70 h - - - - 000e74 h - - - - 000e78 h - - - - 000e7c h - - - - 000e80 h - - - - 000e84 h | 000ebc h - - - - reserve d
document number: 002- 0466 5 rev * a page 96 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000ec0 h - pper01[r/w] b,h 00000000 pper02[r/w] b,h 00000000 pper03[r/w] b,h 00000000 port pull - up/down enable register 000ec4 h pper04[r/w] b,h 00000000 pper05[r/w] b,h - 0000000 - pper07[r/w] b,h -----000 000ec8 h - pper09[r/w] b,h ---00--- - - 000ecc h - - - - 000ed0 h | 000edc h - - - - reserved 000ee0 h - pilr01[r/w] b,h 11111111 pilr02[r/w] b,h 11111111 pilr03[r/w] b,h 11111111 port input level selection register 000ee4 h pilr04[r/w] b,h 11111111 pilr05[r/w] b,h - 1111111 - pilr07[r/w] b,h -----111 000ee8 h - pilr09[r/w] b,h ---11--- - - 000eec h - - - - 000ef0 h | 000efc h - - - - reserved 000f00 h | 000f1c h - - - - reserved 000f20 h - podr01[r/w] b,h 00000000 podr02[r/w] b,h 00000000 podr03[r/w] b,h 00000000 port output drive register 0 00f24 h podr04[r/w] b,h 00000000 podr05[r/w] b,h - 0000000 - podr07[r/w] b,h -----000 000f28 h - podr09[r/w] b,h ---00--- - - 000f2c h - - - - 000f30 h | 000f3c h - - - - reserved 000f40 h porten[r/w] b,h,w ------00 - - - port input enable register 000f44 h keycdr[r/w] h 00000000 00000000 - - port key code 000f48 h aderh[r/w] b,h -------- ---11 --- aderl[r/w] b,h - 1111111 11111111 analog input enable register 000f4c h daer[r/w] b,h -------0 - - - analog output enable register
document number: 002- 0466 5 rev * a page 97 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 000f50 h | 000ffc h - - - - reser ved 001000 h sacr[r/w] b,h,w -------0 picd[r/w] b,h,w ----0011 - - synchronous/asyn chronous switch control 001004 h | 0010bc h - - - - reserved 0010c0 h - - - crccr[r/w] b,h,w - 0000000 crc arithmetic operation 0 0010c4 h crcinit[r/w] b,h,w 11111111 1111111 1 11111111 11111111 0010c8 h crcin[r/w] b,h,w 00000000 00000000 00000000 00000000 0010cc h crcr[r] b,h,w 11111111 11111111 11111111 11111111 0010d0 h - - - crccr1[r/w] b,h,w - 0000000 crc arithmetic operation 1 0010d4 h crcinit1[r/w] b,h,w 11111111 11111 111 11111111 11111111 0010d8 h crcin1[r/w] b,h,w 00000000 00000000 00000000 00000000 0010dc h crcr1[r] b,h,w 11111111 11111111 11111111 11111111 0010e0 h | 0010fc h - - - - reserved 001100 h tcgs[r/w] b,h,w ------00 - - tcgse[r/w] b,h,w --000000 free - run timer simultaneous activation 001104 h cpclrb0/cpclr0[r/w] h,w 11111111 11111111 tcdt0[r/w] h,w 00000000 00000000 free - run timer 0 001108 h tccs0[r/w] b,h,w 00000000 01000000 ----0000 -------- 00110c h cpclrb1/cpclr1[r/w] h,w 11111111 11111111 tcdt1[r/w] h,w 00000000 00000000 free - run timer 1 001110 h tccs1[r/w] b,h,w 00000000 01000000 ----0000 -------- 001114 h cpclrb2/cpclr2[r/w] h,w 11111111 11111111 tcdt2[r/w] h,w 00000000 00000000 free - run timer 2 001118 h tccs2[r/w] b,h,w 00000000 01000000 ----0000 --------
document number: 002- 0466 5 rev * a page 98 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00111c h cpclrb3/cpclr3[r/w] h,w 11111111 11111111 tcdt3[r/w] h,w 00000000 00000000 free - run timer 3 001120 h tccs3[r/w] b,h,w 00000000 01000000 ----0000 -------- 001124 h cpclrb4/cpclr4[r/w] h,w 11111111 11111111 tcdt4[r/w] h,w 00000000 00000000 free - run timer 4 001128 h tccs4[r/w] b,h,w 00000000 01000000 ----0000 -------- 00112c h cpclrb5/cpclr5[r/w] h,w 11111111 11111111 tcdt5[r/w] h,w 00000000 00000000 free - run timer 5 001130 h tccs5[r/w] b,h,w 00000000 01000000 ----0000 -------- 001134 h frs0[r/w] b,h,w -------- - 000- 000 - 000- 000 - 000 - 000 free - run timer selection 001138 h frs1[r/w] b,h,w -------- -------- - 000- 000 - 000- 000 00113c h frs2[r/w] b,h,w -------- - 000- 000 - 000- 000 - 000 - 000 001140 h - 001144 h frs4[r/w] b,h,w - 000- 000 - 000- 000 - 000- 000 - 000- 000 001148 h frs5[r/w] b,h,w -----000 - 000- 000 - 000- 000 - 000- 000 00114c h frs6[r/w] b,h,w -------- -----000 - 000 ---- -------- 001150 h - 001154 h occpb0/occp0[r/w] h,w 00000000 00000000 occpb1/occp1[r/w] h,w 00000000 00000000 output compa re 0/1 001158 h ocs01[r/w] b,h,w - 110--00 00001100 - ocmod01[r/w] b,h,w ------00 00115c h occpb2/occp2[r/w] h,w 00000000 00000000 occpb3/occp3[r/w] h,w 00000000 00000000 output compare 2/3 001160 h ocs23[r/w] b,h,w - 110--00 00001100 - ocmod23[r/w] b,h,w - -----00 001164 h occpb4/occp4[r/w] h,w 00000000 00000000 occpb5/occp5[r/w] h,w 00000000 00000000 output compare 4/5 001168 h ocs45[r/w] b,h,w - 110--00 00001100 - ocmod45[r/w] b,h,w ------00
document number: 002- 0466 5 rev * a page 99 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00116c h occpb6/occp6[r/w] h,w 00000000 00000000 occpb7/o ccp7[r/w] h,w 00000000 00000000 output compare 6/7 001170 h ocs67[r/w] b,h,w - 110--00 00001100 - ocmod67[r/w] b,h,w ------00 001174 h occpb8/occp8[r/w] h,w 00000000 00000000 occpb9/occp9[r/w] h,w 00000000 00000000 output compare 8/9 001178 h ocs89[r/w] b, h,w - 110--00 00001100 - ocmod89[r/w] b,h,w ------00 00117c h occpb10/occp10[r/w] h,w 00000000 00000000 occpb11/occp11[r/w] h,w 00000000 00000000 output compare 10/11 001180 h ocs1011[r/w] b,h,w - 110--00 00001100 - ocmod1011 [r/w] b,h,w ------00 001184 h ipcp0[r] h,w 00000000 00000000 ipcp1[r] h,w 00000000 00000000 input capture 0/1 001188 h ics01[r/w] b,h,w ------ 00 00000000 - lsyns[r/w] b,h,w ------00 00118c h ipcp2[r] h,w 00000000 00000000 ipcp3[r] h,w 00000000 00000000 input capture 2/3 001190 h ic s23[r/w] b,h,w ------ 00 00000000 - - 001194 h - - reserved 001198 h - - - 00119c h - - reserved 0011a0 h - - - 0011a4 h dtsr[r/w] b,h,w ------10 - - - dtti selection 0011a8 h tmrr0[r/w] h,w 00000000 00000001 tmrr1[r/w] h,w 00000000 00000001 waveform gen erator 0/1/2 0011ac h tmrr2[r/w] h,w 00000000 00000001 - - 0011b0 h dtscr0[r/w] b,h,w 00000000 dtscr1[r/w] b,h,w 00000000 dtscr2[r/w] b,h,w 00000000 - 0011b4 h - dtir0[r/w] b,h,w 000000-- - dtmns0[r/w] b,h,w 00---000 0011b8 h - sigcr10[r/w] b,h,w 00000000 - sigcr20[r/w] b,h,w 000000- 1 0011bc h pics0[r/w] b,h,w 000000-- -------- -------- --------
document number: 002- 0466 5 rev * a page 100 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 0011c0 h tmrr3[r/w] h,w 00000000 00000001 tmrr4[r/w] h,w 00000000 00000001 waveform generator 3/4/5 0011c4 h tmrr5[r/w] h,w 00000000 00000001 - - 0011c8 h dts cr3[r/w] b,h,w 00000000 dtscr4[r/w] b,h,w 00000000 dtscr5[r/w] b,h,w 00000000 - 0011cc h - dtir1[r/w] b,h,w 000000-- - dtmns1[r/w] b,h,w 00---000 0011d0 h - sigcr11[r/w] b,h,w 00000000 - sigcr21[r/w] b,h,w -------1 0011d4 h -
document number: 002- 0466 5 rev * a page 101 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 0011d8 h - - - - 12- bit a/d converter 0011dc h adtss[r/w] b,h,w -------0 - - - 0011e0 h adtse[r/w] b,h,w -------- ---00 --- - 0000000 00000000 0011e4 h adcomp0/adcompb0[r/w] h,w 00000000 00000000 adcomp1/adcompb1[r/w] h,w 00000000 00000000 0011e 8 h adcomp2/adcompb2[r/w] h,w 00000000 00000000 adcomp3/adcompb3[r/w] h,w 00000000 00000000 0011ec h adcomp4/adcompb4[r/w] h,w 00000000 00000000 adcomp5/adcompb5[r/w] h,w 00000000 00000000 0011f0 h adcomp6/adcompb6[r/w] h,w 00000000 00000000 adcomp7/adcom pb7[r/w] h,w 00000000 00000000 0011f4 h adcomp8/adcompb8[r/w] h,w 00000000 00000000 adcomp9/adcompb9[r/w] h,w 00000000 00000000 0011f8 h adcomp10/adcompb10[r/w] h,w 00000000 00000000 adcomp11/adcompb11[r/w] h,w 00000000 00000000 0011fc h adcomp12/adcomp b12[r/w] h,w 00000000 00000000 adcomp13/adcompb13[r/w] h,w 00000000 00000000 001200 h adcomp14/adcompb14[r/w] h,w 00000000 00000000 - 001204 h - - 001208 h - adcomp19/adcompb19[r/w] h,w 00000000 00000000 00120c h adcomp20/adcompb20[r/w] h,w 00000000 00000000 - 001210 h - - 001214 h - - - - 001218 h - - - - 00121c h - - - - 001220 h - - - - 001224 h adtcs0[r/w] b,h,w 00000000 0010- 000 adtcs1[r/w] b,h,w 00000000 0010- 000 001228 h adtcs2[r/w] b,h,w 00000000 0010- 000 adtcs3[r/w] b,h,w 00000000 0010- 0 00 00122c h adtcs4[r/w] b,h,w 00000000 0010- 000 adtcs5[r/w] b,h,w 00000000 0010- 000 001230 h adtcs6[r/w] b,h,w 00000000 0010- 000 adtcs7[r/w] b,h,w 00000000 0010- 000
document number: 002- 0466 5 rev * a page 102 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 001234 h adtcs8[r/w] b,h,w 00000000 0010- 000 adtcs9[r/w] b,h,w 00000000 0010- 000 12- bit a/d converter 001238 h adtcs10[r/w] b,h,w 00000000 0010- 000 adtcs11[r/w] b,h,w 00000000 0010- 000 00123c h adtcs12[r/w] b,h,w 00000000 0010- 000 adtcs13[r/w] b,h,w 00000000 0010- 000 001240 h adtcs14[r/w] b,h,w 00000000 0010- 000 - 001244 h - - 001248 h - adtcs19[r/w] b,h,w 00000000 00100000 00124c h adtcs20[r/w] b,h,w 00000000 00100000 - 001250 h - - 001254 h - - - - 001258 h - - - - 00125c h - - - - 001260 h - - - - 001264 h adtcd0[r] b,h,w 10--0000 00000000 adtcd1[r] b,h,w 10--0000 00000000 001268 h adtcd2[r] b,h,w 10--0000 00000000 adtcd3[r] b,h,w 10--0000 00000000 00126c h adtcd4[r] b,h,w 10--0000 00000000 adtcd5[r] b,h,w 10--0000 00000000 001270 h adtcd6[r] b,h,w 10--0000 00000000 adtcd7[r] b,h,w 10--0000 00000000 001274 h adtcd8[r] b ,h,w 10--0000 00000000 adtcd9[r] b,h,w 10--0000 00000000 001278 h adtcd10[r] b,h,w 10--0000 00000000 adtcd11[r] b,h,w 10--0000 00000000 00127c h adtcd12[r] b,h,w 10--0000 00000000 adtcd13[r] b,h,w 10--0000 00000000 001280 h adtcd14[r] b,h,w 10--0000 00000000 - 001284 h - - 001288 h - adtcd19[r] b,h,w 10--0000 00000000 00128c h adtcd20[r] b,h,w 10--0000 00000000 - 001290 h - - 001294 h - - - - 001298 h - - - -
document number: 002- 0466 5 rev * a page 103 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00129c h - - - - 12- bit a/d converter 0012a0 h - - - - 0012a4 h adcs0[r/w] b,h,w 0 ------- -------- adch0[r] b,h,w -----000 admd0[r/w] b,h,w ----0000 0012a8 h adcs1[r/w] b,h,w 0 ------- -------- adch1[r] b,h,w -----000 admd1[r/w] b,h,w ----0000 0012ac h adcs2[r/w] b,h,w 0 ------- -------- adch2[r] b,h,w -----000 admd2[r/w] b,h,w - ---0000 0012b0 h mtrcsr[r/w] b,h,w -------0 - - - motor control extension function 0012b4 h rtosel0[r/w] b,h,w --000000 rtosel1[r/w] b,h,w -------0 - - 0012b8 h | 0012fc h - - - - reserved 001300 h - - - - reserved 001304 h - - - - 001308 h - - - - 00130c h - - - - 001310 h - - - - 001314 h - - - - 001318 h - - - - 00131c h - - - - 001320 h - - - - 001324 h - - 001328 h | 00132c h - - - - 001330 h - - 001334 h | 0013fc h - - - - reserved 001400 h dacr[r/w] b,h,w -------0 - dadr[r/w] h,w ------ xx xxxxxxxx dac 001404 h | 0014fc h - - - - reserved
document number: 002- 0466 5 rev * a page 104 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 001500 h scr0/(ibcr0) [r/w] b,h,w 0 --00000 smr0 [r/w] b,h,w 000000- 0 ssr0 [r/w] b,h,w 0 --00011 escr0/(ibsr0) [r/w] b,h,w 00000000 multi function serial i/f 0 *1 : byte access is possible only for access to lo wer 8 bits. *2 : reserved because i 2 c mode is not set immediately after reset *3 : reserved because csio mode is not set immediately after reset *4 : reserved because lin2.1 mode is not set immediately after reset 001504 h - /(rdr10/(tdr10))[r/w] b,h,w ------- - -------- *3 rdr00/(tdr00)[r/w] b,h,w ------- 0 00000000 *1 001508 h sacsr0[r/w] b,h,w 0 ----000 00000000 stmr0[r] b,h,w 00000000 00000000 00150c h stmcr0[r/w] b,h,w 00000000 00000000 - /(sfur0) [r/w] b,h,w -------- -------- *4 001510 h - - - /(sflr10) [r/ w] b,h,w -------- *4 - /(sflr00) [r/w] b,h,w -------- *4 001514 h - - - - 001518 h - - - - 00151c h bgr0[r/w] h,w 00000000 00000000 - /(ismk0)[r/w] b,h,w -------- *2 - /(isba0)[r/w] b,h,w -------- *2 001520 h fcr10[r/w] b,h,w 00- 00100 fcr00[ r/w ] b,h,w - 0000000 fbyte20[r/w] b,h,w 00000000 fbyte10[r/w] b,h,w 00000000 001524 h scr1[r/w] b,h,w 0 --00000 smr1[r/w] b,h,w 000000- 0 ssr1[r/w] b,h,w 0 --00011 escr1[r/w] b,h,w 00000000 multi function serial i/f 1 *1 : byte access is possible only for access to lower 8 bits. *3 : reserved because csio mode is not set immediately after reset *4 : reserved because lin2.1 mode is not set immediately after reset 001528 h - /(rdr11/(tdr11))[r/w] b,h,w -------- -------- *3 rdr01/(tdr01)[r/w] b,h,w ------- 0 00000000 *1 00152c h s acsr1[r/w] b,h,w 0 ----000 00000000 stmr1[r] b,h,w 00000000 00000000 001530 h stmcr1[r/w] b,h,w 00000000 00000000 - /(scscr1/sfur1) [r/w] b,h,w -------- -------- *3 *4 001534 h - /(scstr31) [r/w] b,h,w -------- *3 - /(scstr21) [r/w] b,h,w -------- *3 - /(scst r11/ sflr11) [r/w] b,h,w -------- *3 *4 - /(scstr01/ sflr01) [r/w] b,h,w -------- *3 *4 001538 h - - - - 00153c h - - - tbyte01[r/w] b,h,w 00000000 001540 h bgr1[r/w] h,w 00000000 00000000 - - 001544 h fcr11[r/w] b,h,w 00- 00100 fcr01[ r/w ] b,h,w - 0000000 fbyte21[r/w] b,h,w 00000000 fbyte11[r/w] b,h,w 00000000 001548 h | 001ffc h - - - - reserved
document number: 002- 0466 5 rev * a page 105 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 002000 h ctrlr0[r/w] b,h,w -------- 000- 0001 statr0[r/w] b,h,w -------- 00000000 can 0 64msb 002004 h errcnt0 [r] b,h,w 00000000 00000000 btr0[r/w] b,h,w - 0100011 00000001 002008 h intr0[r] b,h,w 00000000 00000000 testr0[r/w] b,h,w -------- x00000 -- 00200c h brper0[r/w] b,h,w -------- ----0000 - 002010 h if1creq0[r/w] b,h,w 0 ------- 00000001 if1cmsk0[r/w] b,h,w -------- 00000000 002014 h if1msk20[r/w] b,h,w 11- 11111 11111111 if1msk10[r/w] b,h,w 11111111 11111111 002018 h if1arb20[r/w] b,h,w 00000000 00000000 if1arb10[r/w] b,h,w 00000000 00000000 00201c h if1mctr0[r/w] b,h,w 00000000 0---0000 - 002020 h if1dta10[r/w] b,h,w 00000000 00000000 if1dta20[r /w] b,h,w 00000000 00000000 002024 h if1dtb10[r/w] b,h,w 00000000 00000000 if1dtb20[r/w] b,h,w 00000000 00000000 002028 h , 00202c h - - 002030 h , 002034 h reserved (if1 data mirror) 002038 h , 00203c h - - 002040 h if2creq0[r/w] b,h,w 0 ------- 00000001 if 2cmsk0[r/w] b,h,w -------- 00000000 002044 h if2msk20[r/w] b,h,w 11- 11111 11111111 if2msk10[r/w] b,h,w 11111111 11111111 002048 h if2arb20[r/w] b,h,w 00000000 00000000 if2arb10[r/w] b,h,w 00000000 00000000 00204c h if2mctr0[r/w] b,h,w 00000000 0---0000 - 002050 h if2dta10[r/w] b,h,w 00000000 00000000 if2dta20[r/w] b,h,w 00000000 00000000 002054 h if2dtb10[r/w] b,h,w 00000000 00000000 if2dtb20[r/w] b,h,w 00000000 00000000 002058 h , 00205c h - - 002060 h , 002064 h reserved (if2 data mirror)
document number: 002- 0466 5 rev * a page 106 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 002068 h | 0 0207c h - - can 0 64msb 002080 h treqr20[r] b,h,w 00000000 00000000 treqr10[r] b,h,w 00000000 00000000 002084 h treqr40[r] b,h,w 00000000 00000000 treqr30[r] b,h,w 00000000 00000000 002088 h - - 00208c h - - 002090 h newdt20[r] b,h,w 00000000 00000000 n ewdt10[r] b,h,w 00000000 00000000 002094 h newdt40[r] b,h,w 00000000 00000000 newdt30[r] b,h,w 00000000 00000000 002098 h - - 00209c h - - 0020a0 h intpnd20[r] b,h,w 00000000 00000000 intpnd10[r] b,h,w 00000000 00000000 0020a4 h intpnd40[r] b,h,w 00000000 00000000 intpnd30[r] b,h,w 00000000 00000000 0020a8 h - - 0020ac h - - 0020b0 h msgval20[r] b,h,w 00000000 00000000 msgval10[r] b,h,w 00000000 00000000 0020b4 h msgval40[r] b,h,w 00000000 00000000 msgval30[r] b,h,w 00000000 00000000 0020b8 h - - 0020bc h - - 0020c0 h | 0020fc h - - 002100 h | 0022fc h - - reserved 002300 h dfctlr[r/w] b,h,w - 0 ------ -------- - dfstr[r/w] b,h,w -----001 workflash 002304 h - - - - 002308 h flifctlr[r/w] b,h,w ---0 --00 - fliffer1[r/w] b,h,w -------- fliffer2[r/w] b ,h,w -------- 00230c h | 002ffc h - - - - reserved
document number: 002- 0466 5 rev * a page 107 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 003000 h seearx[r] b,h,w --000000 00000000 deearx[r] b,h,w --000000 00000000 xbs ram ecc control register 003004 h eecsrx[r/w] b,h,w ----00- 0 - efearx[r/w] b,h,w --000000 00000000 003008 h - efecrx[r/w] b ,h,w ------- 0 00000000 00000000 00300c h tear0x[r] b,h,w 000----- -------- -- 000000 00000000 xbs ram diagnosis register 003010 h tear1x[r] b,h,w 000----- -------- -- 000000 00000000 003014 h tear2x[r] b,h,w 000----- -------- -- 000000 00000000 003018 h ta earx[r/w] b,h,w --101111 11111111 tasarx[r/w] b,h,w --000000 00000000 00301c h tfecrx[r/w] b,h,w ----0000 ticrx[r/w] b,h,w ----0000 ttcrx[r/w] b,h,w ------ 00 00001100 003020 h tsrcrx[r/w] b,h,w 0 ------- - - tkccrx[r/w] b,h,w 00----00 003024 h seeara[r] b,h,w --000000 00000000 deeara[r] b,h,w --000000 00000000 backup ram ecc control register 003028 h eecsra[r/w] b,h,w ----00- 0 - efeara[r/w] b,h,w --000000 00000000 00302c h - efecra[r/w] b,h,w ------- 0 00000000 00000000 003030 h tear0a[r] b,h,w 000----- -------- ----- 000 00000000 backup ram diagnosis register 003034 h tear1a[r] b,h,w 000----- -------- ----- 000 00000000 003038 h tear2a[r] b,h,w 000----- -------- ----- 000 00000000 00303c h taeara[r/w] b,h,w -----111 11111111 tasara[r/w] b,h,w -----000 00000000 003040 h tfecra[r/w] b,h,w ----0000 ticra[r/w] b,h,w ----0000 ttcra[r/w] b,h,w ------ 00 00001100 003044 h tsrcra[r/w] b,h,w 0 ------- - - tkccra[r/w] b,h,w 00----00 003048 h | 0030fc h - - - - reserved
document number: 002- 0466 5 rev * a page 108 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 003100 h busdigsr0[r/w] h,w 00000000 0-----0 0 busdigsr1[r/w] h,w 00000000 0-----00 bus diagnosis 003104 h busdigsr2[r/w] h,w 00000000 0-----00 buststr0[r/w] h,w 00--0000 00000000 003108 h busadr0[r] w 00000000 00000000 00000000 00000000 00310c h busadr1[r] w 00000000 00000000 00000000 00000000 0 03110 h busadr2[r] w 00000000 00000000 00000000 00000000 003114 h - busdigsr3[r/w] h,w 00000000 0-----00 003118 h busdigsr4[r/w] h,w 00000000 0-----00 buststr1[r/w] h,w 00--0000 00000000 00311c h - 003120 h busadr3[r] w 00000000 00000000 00000000 000000 00 003124 h busadr4[r] w 00000000 00000000 00000000 00000000 003128 h | 003ffc h - - - - reserved 004000 h | 005ffc h backup ram backup ram area 006000 h | 00cffc h - - - - reserved 00d000 h cif0[r] w 00000100 11111111 01011011 11111111 flexray cif *5 00d0 04 h cif1[r/w] w 00000000 ------- 0 - 0000000 -------- 00d008 h | 00d00c h - - - - reserved 00d010 h - flexray gif *5 00d014 h - 00d018 h - - - - 00d01c h lck[r/w] w -------- -------- -------- 00000000
document number: 002- 0466 5 rev * a page 109 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d020 h eir[r/w] w -----000 ----- 000 ---- 0000 00 000000 flexray int *5 00d024 h sir[r/w] w ------00 ------ 00 00000000 00000000 00d028 h eils[r/w] w -----000 ----- 000 ---- 0000 00000000 00d02c h sils[r/w] w ------11 ------ 11 11111111 11111111 00d030 h eies[r/w] w -----000 ----- 000 ---- 0000 00000000 00 d034 h eier[r/w] w -----000 ----- 000 ---- 0000 00000000 00d038 h sies[r/w] w ------00 ------ 00 00000000 00000000 00d03c h sier[r/w] w ------00 ------ 00 00000000 00000000 00d040 h ile[r/w] w -------- -------- -------- ------ 00 00d044 h t0c[r/w] w --000000 00000000 - 0000000 ------ 00 00d048 h t1c[r/w] w --000000 00000010 -------- ------ 00 00d04c h stpw1[r/w] w --000000 00000000 --000000 - 0000000 00d050 h stpw2[r] w -----000 00000000 ----- 000 00000000 00d054 h | 00d07c h - - - - reserved 00d080 h succ1[r/w ] w ----1100 01000000 00010- 00 1 --- 0000 flexray suc *5 00d084 h succ2[r/w] w ----0001 --- 00000 00000101 00000100 00d088 h succ3[r/w] w -------- -------- -------- 00010001 00d08c h nemc[r/w] w -------- -------- -------- ---- 0000 flexray nem *5 00d090 h pr tc1[r/w] w 000010- 0 01001100 0000- 110 00110011 flexray prt *5 00d094 h prtc2[r/w] w --001111 00101101 --001010 -- 001110 00d098 h mhdc[r/w] w ---00000 00000000 -------- - 0000000 flexray mhd *5
document number: 002- 0466 5 rev * a page 110 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d09c h - reserved 00d0a0 h gtuc1[r/w] w -------- ----0000 000 00010 10000000 flexray gtu *5 00d0a4 h gtuc2[r/w] w -------- ----0010 -- 000000 00001010 00d0a8 h gtuc3[r/w] w - 0000010 - 0000010 00000000 00000000 00d0ac h gtuc4[r/w] w --000000 00001000 -- 000000 00000111 00d0b0 h gtuc5[r/w] w 00001110 ---00000 00000000 00000000 00d0b4 h gtuc6[r/w] w -----000 00000010 ----- 000 00000000 00d0b8 h gtuc7[r/w] w ------ 00 00000010 ------ 00 00000100 00d0bc h gtuc8[r/w] w ---00000 00000000 -------- -- 000010 00d0c0 h gtuc9[r/w] w -------- ------ 00 ---00001 --000001 00d0c4 h g tuc10[r/w] w -----000 00000010 -- 000000 00000101 00d0c8 h gtuc11[r/w] w -----000 ----- 000 ------ 00 ------ 00 00d0cc h | 00d0fc h - reserved 00d100 h ccsv[r] w --000000 00010000 - 100-- 00 00000000 flexray suc *5 00d104 h ccev[r] w -------- -------- ---00000 00-- 0000 00d108 h 00d10c h - reserved
document number: 002- 0466 5 rev * a page 111 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d110 h scv[r] w -----000 00000000 ----- 000 00000000 flexray gtu *5 00d114 h mtccv[r] w -------- --000000 -- 000000 00000000 00d118 h rcv[r] w -------- -------- ---- 0000 00000000 00d11c h ocv[r] w -------- ----- 000 00000000 00000000 00d120 h sfs[r] w -------- ---- 0000 00000000 00000000 00d124 h swnit[r] w -------- -------- ---- 0000 00000000 00d128 h acs[r/w] w -------- -------- ---00000 --- 00000 00d12c h - 00d130 h esid1[r] w -------- -------- 00---- 00 00000000 00d134 h esid2[r] w -------- -------- 00---- 00 00000000 00d138 h esid3[r] w -------- -------- 00---- 00 00000000 00d13c h esid4[r] w -------- -------- 00---- 00 00000000
document number: 002- 0466 5 rev * a page 112 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d140 h esid5[r] w -------- -------- 00----00 000 00000 flexray gtu *5 00d144 h esid6[r] w -------- -------- 00---- 00 00000000 00d148 h esid7[r] w -------- -------- 00---- 00 00000000 00d14c h esid8[r] w -------- -------- 00---- 00 00000000 00d150 h esid9[r] w -------- -------- 00---- 00 00000000 00d154 h esid10[r] w -------- -------- 00---- 00 00000000 00d158 h esid11[r] w -------- -------- 00---- 00 00000000 00d15c h esid12[r] w -------- -------- 00---- 00 00000000 00d160 h esid13[r] w -------- -------- 00---- 00 00000000 00d164 h esid14[r] w -------- - ------- 00---- 00 00000000 00d168 h esid15[r] w -------- -------- 00---- 00 00000000 00d16c h - 00d170 h osid1[r] w -------- -------- 00---- 00 00000000 00d174 h osid2[r] w -------- -------- 00---- 00 00000000 00d178 h osid3[r] w -------- -------- 00----0 0 00000000 00d17c h osid4[r] w -------- -------- 00---- 00 00000000 00d180 h osid5[r] w -------- -------- 00---- 00 00000000 00d184 h osid6[r] w -------- -------- 00---- 00 00000000 00d188 h osid7[r] w -------- -------- 00---- 00 00000000 00d18c h osid8[r ] w -------- -------- 00---- 00 00000000 00d190 h osid9[r] w -------- -------- 00---- 00 00000000 00d194 h osid10[r] w -------- -------- 00---- 00 00000000
document number: 002- 0466 5 rev * a page 113 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d198 h osid11[r] w -------- -------- 00---- 00 00000000 flexray gtu *5 00d19c h osid12[r] w ------- - -------- 00---- 00 00000000 00d1a0 h osid13[r] w -------- -------- 00---- 00 00000000 00d1a4 h osid14[r] w -------- -------- 00---- 00 00000000 00d1a8 h osid15[r] w -------- -------- 00---- 00 00000000 00d1ac h - reserved 00d1b0 h nmv1[r] w 00000000 0000 0000 00000000 00000000 flexray nem *5 00d1b4 h nmv2[r] w 00000000 00000000 00000000 00000000 00d1b8 h nmv3[r] w 00000000 00000000 00000000 00000000 00d1bc h | 00d2fc h - reserved
document number: 002- 0466 5 rev * a page 114 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d300 h mrc[r/w] w ----- 001 10000000 00000000 00000000 flexray mhd *5 00d304 h frf[r/w] w ------- 1 10000000 --- 00000 00000000 00d308 h frfm[r/w] w -------- -------- ---00000 000000-- 00d30c h fcl[r/w] w -------- -------- -------- 10000000 00d310 h mhds[r/w] w - 0000000 - 0000000 - 0000000 0 0000000 00d31 4 h ldts[r] w -----000 00000000 ----- 000 00000000 00d318 h fsr[r] w -------- -------- 00000000 ----- 000 00d31c h mhdf[r/w] w -------- -------- ------- 0 00000000 00d320 h txrq1[r] w 00000000 00000000 00000000 00000000 00d324 h txrq2[r] w 00000000 0000000 0 00000000 00000000 00d328 h txrq3[r] w 00000000 00000000 00000000 00000000 00d32c h txrq4[r] w 00000000 00000000 00000000 00000000 00d330 h ndat1[r] w 00000000 00000000 00000000 00000000 00d334 h ndat2[r] w 00000000 00000000 00000000 00000000 00d338 h ndat3[r] w 00000000 00000000 00000000 00000000 00d33c h ndat4[r] w 00000000 00000000 00000000 00000000 00d340 h mbsc1[r] w 00000000 00000000 00000000 00000000 00d344 h mbsc2[r] w 00000000 00000000 00000000 00000000 00d348 h mbsc3[r] w 00000000 000000 00 00000000 00000000 00d34c h mbsc4[r] w 00000000 00000000 00000000 00000000 00d350 h | 00d3ec h - reserved
document number: 002- 0466 5 rev * a page 115 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d3f0 h crel[r] w 00010000 00111001 00000010 00000110 flexray gif *5 00d3f4 h endn[r] w 10000111 01100101 01000011 00100001 00d3f8 h | 00d3fc h - reserved 00d400 h | 00d4fc h wrdsn[1 - 64][r/w] w 00000000 00000000 00000000 00000000 flexray ibf *5 00d500 h wrhs1[r/w] w --000000 - 0000000 ----- 000 00000000 00d504 h wrhs2[r/w] w -------- - 0000000 ----- 000 00000000 00d508 h wrhs3[r/w] w -------- -------- ----- 000 00000000 00d50c h - 00d510 h ibcm[r/w] w -------- ------ 00 -------- -----000 00d514 h ibcr[r/w] w 0 ------- - 0000000 0 ------- - 0000000 00d518 h | 00d5fc h - reserved 00d600 h | 00d6fc h rddsn[1 - 64][r] w 00000000 00000000 00000000 00000000 flexray obf *5 00d700 h rdhs1[r] w --000000 - 0000000 ----- 000 00000000 00d704 h rdhs2[r] w - 0000000 - 0000000 ----- 000 00000000 00d708 h rdhs3[r] w --000000 --000000 ----- 000 00000000 00d70c h mbs[r] w --000000 --000000 00- 00000 00000000 00d710 h obcm[r/w] w - ------- ------ 00 -------- ------00 00d714 h obcr[r/w] w -------- - 0000000 0 -----00 - 0000000 00d718 h | 00d7fc h - reserved
document number: 002- 0466 5 rev * a page 116 of 175 mb91580m/s series address address offset value/register name block +0 +1 +2 +3 00d800 h | 00effc h - reserved 00f000 h | 00fefc h - reserved [s] 00ff00 h dsucr[r/w] b,h,w -------- ------- 0 - - ocdu [s] 00ff04 h | 00ff0c h - - - - reserved [s] 00ff10 h pcsr[r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00ff14 h pssr[r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00ff18 h | 00fff4 h - - - - reserved [s] 00fff8 h edir1[r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxx xxxx ocdu [s] 00fffc h edir0[r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx [s]: it is a system register. the illegal instruction exception (data access error) is generated when reading and writing to these registers in the user mode. *5: for flexray, the mb91f583 a sg/f584a sg/f585 a sg/f583 a sj/f584a sj/f585 a sj has corresponding functions. the following registers are reserved registers for models without the flexray function. 000125 h irpr2l[5:4], 000e68 h , 0004e8 h - 0004ef h , 00d000 h - 00d717 h
document number: 002- 0466 5 rev * a page 117 of 175 mb91580m/s series 10. interrupt vector table ? mb91f583 a m/f584a m/f585 a m interrupt factor interrupt number inter rupt level offset tbr default address rn *1 interrupt request batch read target decimal hexa decimal reset 0 00 - 3fc h 000ffffc h - - system reserved 1 01 - 3f8 h 000ffff8 h - - system reserved 2 02 - 3f4 h 000ffff4 h - - system reserved 3 03 - 3f0 h 000ffff0 h - - system reserved 4 04 - 3ec h 000fffec h - - fpu exception 5 05 - 3e8 h 000fffe8 h - - instruction access protection violation exception 6 06 - 3e4 h 000fffe4 h - - data access prot ection violation exception 7 07 - 3e0 h 000fffe0 h - - data access error interrupts 8 08 - 3dc h 000fffdc h - - inte instruction 9 09 - 3d8 h 000fffd8 h - - instruction break 10 0a - 3d4 h 000fffd4 h - - system reserved 11 0b - 3d0 h 000fffd0 h - - system reser ved 12 0c - 3cc h 000fffcc h - - system reserved 13 0d - 3c8 h 000fffc8 h - - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - - nmi request error generation at internal bus diagnosis ram double - bit error backup ram double - bit error 15 0f 15(f h ) fi xed 3c0 h 000fffc0 h - ? external interrupt 0 - 7 16 10 icr0 0 3bc h 000fffbc h 0 - reload timer 0 / 1 17 11 icr0 1 3b8 h 000fffb8 h 1 ? reload timer 2 / 3 18 12 icr0 2 3b4 h 000fffb4 h 2 ? multifunction serial interface ch.0 (reception completed)/ multifunction se rial interface ch.0 (status) 19 13 icr0 3 3b0 h 000fffb0 h 3 *2 ? multifunction serial interface ch.0 (transmission completed) 20 14 icr0 4 3ac h 000fffac h 4 - multifunction serial interface ch.1 (reception completed)/ multifunction serial interface ch.1 (stat us) 21 15 icr0 5 3a8 h 000fffa8 h 5 *2 ? multifunction serial interface ch.1 (transmission completed) 22 16 icr0 6 3a4 h 000fffa4 h 6 - multifunction serial interface ch.2 (reception completed)/ multifunction serial interface ch.2 (status) 23 17 icr0 7 3a0 h 000f ffa0 h 7 *2 ? multifunction serial interface ch.2 (transmission completed) 24 18 icr0 8 39c h 000fff9c h 8 - multifunction serial interface ch.3 (reception completed)/ multifunction serial interface ch.3 (status) 25 19 icr0 9 398 h 000fff98 h 9 *2 ? multifunctio n serial interface ch.3 (transmission completed) 26 1a icr1 0 394 h 000fff94 h 10 - *4 27 1b icr1 1 390 h 000fff90 h - - *4 28 1c icr1 2 38c h 000fff8c h - -
document number: 002- 0466 5 rev * a page 118 of 175 mb91580m/s series interrupt factor interrupt number inter rupt level offset tbr default address rn *1 interrupt request batch read target decimal hexa decimal can 0 29 1d icr1 3 388 h 000fff88 h - - can 1 30 1e icr1 4 384 h 000fff84 h - - flexray 0 * 5 31 1f icr1 5 380 h 000fff80 h - - flexray 1 * 5 32 20 icr1 6 37c h 000fff7c h - - flexray timer 0 * 5 33 21 icr1 7 378 h 000fff78 h - - flexray timer 1 * 5 34 22 icr1 8 374 h 000fff74 h - - ram diagnosis completed ram initialization completed error generation at ram diagnosis backu p ram diagnosis completed backup ram initialization completed error generation at backup ram diagnosis 35 23 icr1 9 370 h 000fff70 h - ? main timer/pll timer/ pll gear for flexray * 5 / pll alarm for flexray * 5 36 24 icr2 0 36c h 000fff6c h 20 *3 ? clock calibratio n unit (cr oscillation) 37 25 icr2 1 368 h 000fff68 h - - u/d counter 0 / 1 38 26 icr2 2 364 h 000fff64 h 22 ? free - run timer 0 (0 detection) / (compare clear) 39 27 icr2 3 360 h 000fff60 h 23 ? free - run timer 1 (0 detection) / (compare clear) 40 28 icr2 4 35c h 000fff5c h 24 ? free - run timer 2 (0 detection) / (compare clear) ppg 0 / 1 / 2 / 3 41 29 icr2 5 358 h 000fff58 h 25 ? free - run timer 3 (0 detection) / (compare clear) 42 2a icr2 6 354 h 000fff54 h 26 ? free - run timer 4 (0 detection) / (compare clear) 43 2b icr2 7 350 h 000fff50 h 27 ? free - run timer 5 (0 detection) / (compare clear) ppg 4 / 5 44 2c icr2 8 34c h 000fff4c h 28 ? icu 0 (fetching) / icu 1 (fetching) 45 2d icr2 9 348 h 000fff48 h 29 ? icu 2 (fetching) / icu 3 (fetching) 46 2e icr3 0 344 h 000fff44 h 30 ? *4 47 2f icr3 1 340 h 000fff40 h - - *4 48 30 icr3 2 33c h 000fff3c h - - ocu 0 (match) / ocu 1 (match) 49 31 icr3 3 338 h 000fff38 h 33 ? ocu 2 (match) / ocu 3 (match) 50 32 icr3 4 334 h 000fff34 h 34 ? ocu 4 (match) / ocu 5 (match) 51 33 icr3 5 330 h 000fff30 h 35 ? ocu 6 (match) / ocu 7 (match) 52 34 icr3 6 32c h 000fff2c h 36 ? ocu 8 (match) / ocu 9 (match) 53 35 icr3 7 328 h 000fff28 h 37 ? ocu 10 (match) / ocu 11 (match) 54 36 icr3 8 324 h 000fff24 h 38 ?
document number: 002- 0466 5 rev * a page 119 of 175 mb91580m/s series interrupt factor interrupt number inter rupt level offset tbr default address rn *1 interrupt request batch read target decimal hexa decimal wg dead timer underflow 0 / 1 / 2 wg dead timer reload 0 / 1 / 2 wg dtti 0 55 37 icr3 9 320 h 000fff20 h 39 ? wg dead timer underflow 3 / 4 / 5 wg dead timer reload 3 / 4 / 5 wg dtti 1 56 38 icr4 0 31c h 000fff1c h 40 ? ad converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 57 39 icr4 1 318 h 000fff18 h 41 ? ad converter 8 / 9 / 10 / 11 / 12 / 13 / 14 58 3a icr4 2 314 h 000fff14 h 42 ? ad converter 16 / 17 / 18 / 19 / 20 / 21 / 22 / 23 59 3b icr4 3 310 h 000fff10 h 43 ? base timer 0 irq 0/ base timer 0 irq 1 60 3c icr4 4 30c h 000fff0c h 44 ? base timer 1 irq 0/ base timer 1 irq 1 61 3d i cr4 5 308 h 000fff08 h 45 ? dmac 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 62 3e icr4 6 304 h 000fff04 h - ? delay interrupt 63 3f icr4 7 300 h 000fff00 h - - system reserved 64 40 - 2fc h 000ffefc h - - system reserved 65 41 - 2f8 h 000ffef8 h - - used with the int instructi on. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - - *1 : does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *2 : the multi - function serial interface status does n ot support dma transfer caused by i 2 c reception. *3 : "pll gear for flexray" and "pll alarm for flexray" do not support dma transfer. * 4 : for mb91f583 a m/f584a m/f585 a m, the interrupt vectors are unused. * 5 : for flexray, the mb91f583 a mg/f584a mg/f585a mg/f583am j/f584 a mj/f585 a mj ha ve corresponding functions.
document number: 002- 0466 5 rev * a page 120 of 175 mb91580m/s series ? mb91f583 a s/f584a s/f585a s interrupt factor interrupt number inter rupt level offset tbr default address rn *1 interrupt request batch read target decimal hexa decimal reset 0 00 - 3fc h 000ffffc h - - sy stem reserved 1 01 - 3f8 h 000ffff8 h - - system reserved 2 02 - 3f4 h 000ffff4 h - - system reserved 3 03 - 3f0 h 000ffff0 h - - system reserved 4 04 - 3ec h 000fffec h - - fpu exception 5 05 - 3e8 h 000fffe8 h - - instruction access protection violation excep tion 6 06 - 3e4 h 000fffe4 h - - data access protection violation exception 7 07 - 3e0 h 000fffe0 h - - data access error interrupts 8 08 - 3dc h 000fffdc h - - inte instruction 9 09 - 3d8 h 000fffd8 h - - instruction break 10 0a - 3d4 h 000fffd4 h - - system r eserved 11 0b - 3d0 h 000fffd0 h - - system reserved 12 0c - 3cc h 000fffcc h - - system reserved 13 0d - 3c8 h 000fffc8 h - - exception of invalid instruction 14 0e - 3c4 h 000fffc4 h - - nmi request error generation at internal bus diagnosis ram double - bit e rror backup ram double - bit error 15 0f 15(f h ) fixed 3c0 h 000fffc0 h - ? external interrupt 0 - 6 16 10 icr0 0 3bc h 000fffbc h 0 - reload timer 0 / 1 17 11 icr0 1 3b8 h 000fffb8 h 1 ? reload timer 2 / 3 18 12 icr0 2 3b4 h 000fffb4 h 2 ? multifunction serial interf ace ch.0 (reception completed)/ multifunction serial interface ch.0 (status) 19 13 icr0 3 3b0 h 000fffb0 h 3 *2 ? multifunction serial interface ch.0 (transmission completed) 20 14 icr0 4 3ac h 000fffac h 4 - multifunction serial interface ch.1 (reception compl eted)/ multifunction serial interface ch.1 (status) 21 15 icr0 5 3a8 h 000fffa8 h 5 *2 ? multifunction serial interface ch.1 (transmission completed) 22 16 icr0 6 3a4 h 000fffa4 h 6 - *4 23 17 icr0 7 3a0 h 000fffa0 h - - *4 24 18 icr0 8 39c h 000fff9c h - - *4 25 1 9 icr0 9 398 h 000fff98 h - -
document number: 002- 0466 5 rev * a page 121 of 175 mb91580m/s series interrupt factor interrupt number inter rupt level offset tbr default address rn *1 interrupt request batch read target decimal hexa decimal *4 26 1a icr1 0 394 h 000fff94 h - - *4 27 1b icr1 1 390 h 000fff90 h - - *4 28 1c icr1 2 38c h 000fff8c h - - can 0 29 1d icr1 3 388 h 000fff88 h - - *4 30 1e icr1 4 384 h 000fff84 h - - flexray 0 * 5 31 1f icr1 5 380 h 000fff80 h - - flexr ay 1 * 5 32 20 icr1 6 37c h 000fff7c h - - flexray timer 0 * 5 33 21 icr1 7 378 h 000fff78 h - - flexray timer 1 * 5 34 22 icr1 8 374 h 000fff74 h - - ram diagnosis completed ram initialization completed error generation at ram diagnosis backup ram diagnosis comple ted backup ram initialization completed error generation at backup ram diagnosis 35 23 icr1 9 370 h 000fff70 h - ? main timer/pll timer/ pll gear for flexray * 5 / pll alarm for flexray * 5 36 24 icr2 0 36c h 000fff6c h 20 *3 ? clock calibration unit (cr oscillation ) 37 25 icr2 1 368 h 000fff68 h - - u/d counter 0 / 1 38 26 icr2 2 364 h 000fff64 h 22 ? free - run timer 0 (0 detection) / (compare clear) 39 27 icr2 3 360 h 000fff60 h 23 ? free - run timer 1 (0 detection) / (compare clear) 40 28 icr2 4 35c h 000fff5c h 24 ? free - run timer 2 (0 detection) / (compare clear) ppg 0 / 1 / 2 / 3 41 29 icr2 5 358 h 000fff58 h 25 ? free - run timer 3 (0 detection) / (compare clear) 42 2a icr2 6 354 h 000fff54 h 26 ? free - run timer 4 (0 detection) / (compare clear) 43 2b icr2 7 350 h 000fff50 h 27 ? free - run timer 5 (0 detection) / (compare clear) ppg 4 / 5 44 2c icr2 8 34c h 000fff4c h 28 ?
document number: 002- 0466 5 rev * a page 122 of 175 mb91580m/s series interrupt factor interrupt number inter rupt level offset tbr default address rn *1 interrupt request batch read target decimal hexa decimal icu 0 (fetching) / icu 1 (fetching) 45 2d icr2 9 348 h 000fff48 h 29 ? icu 2 (fetching) / icu 3 (fetching) 46 2e icr3 0 344 h 000fff44 h 30 ? *4 47 2f icr3 1 340 h 000fff40 h - - *4 48 30 icr3 2 33c h 000fff3c h - - ocu 0 (match) / ocu 1 (match) 49 31 icr3 3 338 h 000fff38 h 33 ? ocu 2 (match) / ocu 3 (match) 50 32 icr3 4 334 h 000fff34 h 34 ? ocu 4 (match) / ocu 5 (match) 51 33 icr3 5 330 h 000fff30 h 35 ? ocu 6 (match) / ocu 7 (match) 52 34 icr3 6 32c h 000fff2c h 36 ? ocu 8 (match) / ocu 9 (match) 53 35 icr3 7 328 h 000fff28 h 37 ? ocu 10 (match) / ocu 11 (match) 54 36 icr3 8 324 h 000fff24 h 38 ? wg dead timer underflow 0 / 1 / 2 wg dead timer reload 0 / 1 / 2 wg dtti 0 55 37 icr3 9 320 h 000fff20 h 39 ? wg dead timer underflow 3 / 4 / 5 wg dead timer reload 3 / 4 / 5 wg dtti 1 56 38 icr4 0 31c h 000fff1c h 40 ? ad converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 57 39 icr4 1 318 h 000fff18 h 41 ? ad converter 8 / 9 / 10 / 11 / 12 / 13 / 14 5 8 3a icr4 2 314 h 000fff14 h 42 ? ad converter 19 / 20 59 3b icr4 3 310 h 000fff10 h 43 ? base timer 0 irq 0/ base timer 0 irq 1 60 3c icr4 4 30c h 000fff0c h 44 ? base timer 1 irq 0/ base timer 1 irq 1 61 3d icr4 5 308 h 000fff08 h 45 ? dmac 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 62 3e icr4 6 304 h 000fff04 h - ? delay interrupt 63 3f icr4 7 300 h 000fff00 h - - system reserved 64 40 - 2fc h 000ffefc h - - system reserved 65 41 - 2f8 h 000ffef8 h - - used with the int instruction. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ff c00 h - -
document number: 002- 0466 5 rev * a page 123 of 175 mb91580m/s series *1 : does not support a dma transfer request caused by an interrupt generated from a peripheral to which no rn (resource number) is assigned. *2 : the multi - function serial interface status does not support dma transfer caused by i 2 c reception. *3 : "pll gear for flexray" and "pll alarm for flexray" do not support dma transfer. * 4 : for mb91f583 a s/f584a s/f585a s, the interrupt vectors are unused. * 5 : for flexray, the mb91f583 a sg/f584a sg/f585 a sg/f583 a sj/f584a sj/f585 a sj ha ve corresponding functions
document number: 002- 0466 5 rev * a page 124 of 175 mb91580m/s series 11. elect rical characteristics 11.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1 , * 2 v cc v ss - 0.3 v ss +6.0 v analog power supply voltage * 1 , * 2 av cc v ss - 0.3 v ss +6.0 v avcc vcc analog reference voltage * 1 avrh v ss - 0.3 v ss +6.0 v avrh av cc input voltage * 1 v i v ss - 0.3 v cc +0.3 v analog pin input voltage * 1 v i a v ss - 0.3 v cc +0.3 v output voltage * 1 v o v ss - 0.3 v cc +0.3 v maximum clamp current i clamp - 4 ma * 9 total maximum clamp current |i clamp | - 20 ma * 9 "l" leve l maximum output current * 3 i ol 1 - 7 ma when setting to 2ma * 6 i ol 2 - 14 ma when setting to 4ma * 7 i ol 3 - 17.5 ma when setting to 5ma * 8 "l" level average output current * 4 i olav 1 - 2 ma when setting to 2ma * 6 i olav 2 - 4 ma when setting to 4ma * 7 i ol av3 - 5 ma when setting to 5ma * 8 "l" level total output current * 5 i ol - 50 ma * 6 "h" level maximum output current * 3 i oh 1 - - 7 ma when setting to 2ma * 6 i oh 2 - - 14 ma when setting to 4ma * 7 i oh 3 - - 17.5 ma when setting to 5ma * 8 "h" level average output current * 4 i ohav 1 - - 2 ma when setting to 2ma * 6 i ohav 2 - - 4 ma when setting to 4ma * 7 i ohav 3 - - 5 ma when setting to 5ma * 8 "h" level total output current * 5 i oh - - 50 ma * 6 power consumption p d - 690 mw operating temperature t a - 40 +125 c * 10, * 1 1 storage temperature tstg - 55 +150 c *1: these parameters are based on the condition that v ss =av ss =0.0v. *2: caution must be taken that av cc does not exceed v cc . *3: the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4: the average output c urrent is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. the average value is the operation current the operation ratio. *5: the total output current is defined as the maximum current val ue flowing through all of corresponding pins. *6: corresponding pins: general - purpose ports *7: corresponding pins: general - purpose ports of p021 to p023, p025 to p027 *8: corresponding pins: general - purpose ports other than those of p021 to p023, p025 to p027
document number: 002- 0466 5 rev * a page 125 of 175 mb91580m/s series *9 : ? corresponding pins: general - purpose ports ? use the devices within recommended operating conditions. ? use the devices with direct voltage (current). ? the + b signal should always be applied by connecting a limiting resistor between the + b signal and t he microcontroller. ? the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + b signal is input. ? note that when the microcontroller drive current is low, such as in the low - power consumption modes, the + b input potential can increase the potential at the vcc pin via a protective diode, possibly affecting other devices. ? note that if the + b signal is input when th e microcontroller is off (not fixed at 0 v), since the power is supplied through the pin, the microcontroller may operate incompletely. ? note that if the +b signal is input at power - on, since the power is supplied through the pin, the power - on reset may n ot function in the power supply voltage. ? do not leave + b input pins open. sample recommended circuit mb91580m/s series +b input (12 to 16v) protective diode limiting resistor current *10: to use this product at t a =125 c , equip this on a multilayer board with four or more layers. to equip this on a single - layer board, change the operating conditions (operating frequency, power supply voltage, etc) to use this at the power consumption p d =415mw or lower, or use this at t a =105 c or lower. *11: when it is used exceeding t a =125 c , contact your sales representative. warning semiconduc tor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings.
document number: 002- 0466 5 rev * a page 126 of 175 mb91580m/s series 11.2 recommended operating conditions (v ss = a v ss =0.0v) parameter symbol value unit remarks min max power supply voltage v cc 4.5 5.5 v recommended operation guarantee range av cc 4.5 5.5 v v cc 3.7 5.5 v operation guarantee range av cc 3.7 5.5 v smoothing capacitor * 1 c s 4.7 (tolerance with in 50%) f use a ceramic capacitor or a capacitor that has the similar frequency characteristics. use a capacitor with a capacitance greater than c s as the smoothing capacitor on the vcc pin. operating temperature t a - 40 +125 c * 2 * 1 : for connection of smoothing capacitor c s , see the figure below. * 2 : when it is used exceeding t a =125 c , contact your sales representative. c pin connection diagram c s c v s s a v s s warning the recommended operating conditions are required in order to ensure the normal operation of th e semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions o ther than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering applicati on under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002- 0466 5 rev * a page 127 of 175 mb91580m/s series 11.3 dc characteristics (t a : recommended operating conditions , vcc=5.0v 10%, v ss = av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih1 p000 to p007 * , p010 to p017, p020, p024, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * when cmos schmitt input lev el is selected 0.7 v cc - v cc +0.3 v v ih2 p000 to p007 * , p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * when automotive input lev el is selected 0.8 v cc - v cc +0.3 v v ih3 p021 to p023, p025 to p027 when flexray input level is selected 0.7 v cc - v cc +0.3 v v ih4 rstx, nmix - 0.7 v cc - v cc +0.3 v v ih5 md0, md1 - 0.7 v cc - v cc +0.3 v v ih6 debugif - 2.0 - v cc +0.3 v *: on ly available with mb91f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 128 of 175 mb91580m/s series (t a : recommended operating conditions , vcc=5.0v 10%, v ss = av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "l" level input voltage v il1 p000 to p007 * , p010 to p017, p 020, p024, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * when cmos schmitt input level is selected vss - 0.3 - 0. 3 v cc v v il2 p000 to p007 * , p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * when automotive input level is selected vss - 0.3 - 0. 5 v cc v v il3 p021 to p023, p025 to p027 wh en flexray input level is selected vss - 0.3 - 0. 3 v cc v v il4 rstx, nmix - vss - 0.3 - 0. 3 v cc v v il5 md0, md1 - vss - 0.3 - 0. 3 v cc v v il6 debugif - vss - 0.3 - 0.8 v *: only available with mb91f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 129 of 175 mb91580m/s series (t a : recommended opera ting conditions , vcc=5.0v 10%,v ss = av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v o h1 p000 to p007 * , p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * vcc=4.5v i o h = - 2.0ma vcc - 0.5 - vcc v v o h2 p021 to p023, p025 to p027 vcc=4.5v i o h = - 4.0ma vcc - 0.5 - vcc v when flexray is selected v o h3 p000 to p007 * , p010 to p017, p020, p024, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * vcc=4.5v i o h = - 5.0ma vcc - 0.5 - vcc v *: only available with mb91f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 130 of 175 mb91580m/s series (t a : recom mended operating conditions , vcc=5.0v 10%, v ss = av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v o l1 p000 to p007 * , p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p056, p060 t o p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * vcc=4.5v i o l =2.0ma 0 - 0.4 v v o l2 p021 to p023, p025 to p027 vcc=4.5v i o l =4.0ma 0 - 0.4 v when flexray is selected v o l3 p000 to p007 * , p010 to p017, p020, p 024, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p093, p094, p095 to p097 * , p100 to p102 * vcc=4.5v i o l =5.0ma 0 - 0.4 v v o l4 p040, p041, p063 * , p064 * , p080 * , p081 * , p083 * ,p084 * vcc=4.5v i o l =3.0ma 0 - 0.4 v i 2 c shared pin (when i 2 c is selected) v o l5 debugif vcc=2.7v i o l =25.0ma 0 - 0.25 v *: only available with mb91f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 131 of 175 mb91580m/s series (t a : recommended operating conditions , vcc=5.0v 10%, v ss = av ss =0.0v) parameter symbol pin name conditi ons value unit remarks min typ max input leak current i i l all input pins vcc = av cc =5.5v v ss < v i < v cc - 5 - +5 a pull - up resistance r up1 rstx, nmix - 25 - 100 k r up2 p000 to p007 * , p010 to p017, p020 to p027, p030 to p037, p040 to p047, p050 to p056, p060 to p066 * , p070 to p072, p080 to p087 * , p090 to p092 * , p0 93, p094, p 095 to p097 * , p100 to p102 * when pull - up resistance is selected 25 - 100 k input capacitor c in other than vcc, vss, avcc, avss, c - - 5 15 pf *: only available with mb9 1f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 132 of 175 mb91580m/s series (t a : recommended operating conditions , vcc=5.0v 10%, v ss = av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max power supply current i cc vcc5 normal operations f cp =128mhz, f cpm =128mhz, f cpp =3 2mhz - 80 110 ma flexray =on - 73 103 ma flexray =off normal operations f cp =128mhz, f cpm =32mhz, f cpp =32mhz - 77 107 ma flexray =on - 70 100 ma flexray =off normal operations f cp =80mhz, f cpm =80mhz, f cpp =40mhz - 62 89 ma flexray =on - 57 85 ma flexray =off normal operations f cp =80mhz, f cpm =40mhz, f cpp =40mhz - 6 1 88 ma flexray =on - 5 6 84 ma flexray =off flash write f cp =128mhz, f cpm =128mhz, f cpp =32mhz - 95 125 ma * flash erase f cp =128mhz, f cpm =128mhz, f cpp =32mhz - 95 125 ma * *: this series has 2 types of flash; main flash and w ork f lash; however, this is the specification when only one of those is written/erased.
document number: 002- 0466 5 rev * a page 133 of 175 mb91580m/s series (t a : recommended operating conditions , vcc=5.0v 10%, v ss = av ss =0.0v) parameter symbol pin name cond itions value unit remarks min typ max power supply current i ccs vcc5 cpu sleep f cp =128mhz, f cpm =128mhz, f cpp =32mhz - 41 66 ma *1, *2 ,*3, *4 i ccbs bus sleep f cp =128mhz, f cpm =128mhz, f cpp =32mhz - 19 4 5 ma *1, *2 ,*3 ,*4 i cct clock mode 4mhz source oscillation - 1.2 1.8 m a when using external clock *5 t a = 25 c, *1, *2 ,*3 ,*4 - 2.7 3.3 m a when using crystal t a = 25 c, *1, *2, *3, *4 i ccts clock mode shutdown 4mhz source oscillation - 0.3 0.4 m a when using external clock *5 t a = 25 c, *1, *2 - 1.8 1.9 m a when using crystal t a = 25 c, *1, *2 - 0.7 0.8 ma when using external clock *5 t a = 25 c, *3, *4 - 2.2 2.3 ma when using crystal t a = 25 c, *3 ,*4 i cch stop mode - 0.6 1.1 m a t a = 25 c, *1 ,*2 - 1.0 1.6 m a t a = 25 c, *3 ,*4 i cchs stop mode shutdown - 0.1 0.2 m a t a = 25 c, *1, *2 - 0.5 0.6 m a t a = 25 c, *3, *4 *1 : m b91f583 a mg/f584a mg/f585 a mg/f583a mh/f584a mh/f585 amh *2 :mb91f583 a sg/f584a sg/f585a sg/f583 a sh/f584 a sh/f585ash *3 :mb91f583 a mj/f584a mj/f585a mj/f583a mk/f584a mk/f585amk *4 :mb 91f583 a sj/f584 a sj/f585a sj/f583 a sk/f584 a sk/f585 ask *5: the power supply current is the current value when the external clock is supplied from the x1 pin. note that the power supply current value when using the external clock is different from that using the oscillator.
document number: 002- 0466 5 rev * a page 134 of 175 mb91580m/s series 11.4 a c characteristics 11.4.1 main clock timing (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max source oscillation clock frequency f c x0, x1 - 4 - 20 mhz source oscillation clock cycle time t cyl x0, x1 - 50 - 250 ns internal operating clock frequency * f c p - - - - 128 mhz cpu clock f c pp - - - - 40 mhz peripheral bus clock f c pm - - - - 128 mhz motor clock internal operating clock cycle time * t c p - - 7.82 - - ns cpu clock t c pp - - 25 - - ns peripheral bus clock t c pm - - 7.82 - - ns motor clock can pll jitter ( during lock) t pj - - - 10 - +10 ns built - in cr oscillation frequency f c cr - - 50 100 150 khz *: the maximum/minimum value is de fined when using the main clock and pll clock. ? x0,x1 clock timing x 0 t cyl
document number: 002- 0466 5 rev * a page 135 of 175 mb91580m/s series ? can pll jitter ideal clock pll output slow fast t1 t2 t3 t1 t2 t3 tn-1 tn tn-1 tn deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. ? guaranteed operation range internal operation clock frequency vs. power supply voltage internal operation clock frequency f cp (mhz) 128 4 2 3.7 5.5 power supply voltage v cc (v) mb91f58x guaranteed operation range pll guaranteed operation range 4.5 mb91f58x recommended guaranteed operation range note: the cpu will be reset at the power supply voltage of the low - voltage detection setting voltage or less.
document number: 002- 0466 5 rev * a page 136 of 175 mb91580m/s series oscillation clock frequency vs. internal operation clock frequency internal operation clock frequency main clock pll clock multipli ed by 1 multipli ed by 2 multipli ed by 3 multipli ed by 4 ... multiplied by 20 ... multiplied by 32 oscillation clock frequency 4mh z 2mh z 4mhz 8mhz 12mhz 16mhz ... 80mhz ... 128mhz ? example of oscillation circuit x1 x0 r=330 c2=12pf c1=12pf 4mhz note: if it is impossible to start the oscillation within or equal to 20ms when starting from the oscillation stop state, the clock supervisor performs a detection of oscillation stop and moves to the fail safe operation. design y our print circuit board so that the oscillator can start oscillation within 20ms. in addition, when configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator manufacturers for the design.
document number: 002- 0466 5 rev * a page 137 of 175 mb91580m/s series ac character istics are specified by the following measurement reference voltage values. input signal waveform output signal waveform hysteresis input pin (automotive) 0.5vcc 0.8vcc output pin 0.8v 2.4v hysteresis input pin (cmos schmitt) 0.3vcc 0.7vcc hysteresis input pin (flexray) 0.35vcc 0.65vcc 11.4.2 reset in put (t a : recommended operating conditions , vcc =5.0v 10%, vss=avss=0. 0v) parameter symbol pin name conditions value unit remarks min max reset input time t rstl rstx - 10 - s during normal operation oscillation time of oscillator * + 0.1 - ms at stop mode 100 - s at clock mode reset input removal width 1 - s *: the oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. for crysta l oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred s and several ms, and for an external clock, the time is 0 ms. rstx 0.2vcc 0.2vcc t rstl
document number: 002- 0466 5 rev * a page 138 of 175 mb91580m/s series in stop mode 0.2 v cc 0.2 v cc 100 s rstx x 0 90% of amplitude internal operation clock oscillation time of oscillator oscillation stabilization waiting time instruction execution internal reset t rstl 11.4.3 power - on conditions (t a : recommended operating conditions , v ss =0.0 v) para meter symbol pin name conditions value unit remarks min typ max level detection voltage - vcc5 - 2.024 2.200 2.376 v when turning on power level detection hysteresis width - vcc5 - - 100 - m v during voltage drop level detection time - - - - - 30 s *1 slope detection undetected standard - vcc5 v cc =level detection release level - - 4 mv/ s *2 power off time t off vcc5 - 50 - - ms * 3 *1: if the fluctuation o f the power supply is faster than the low - voltage detection time, there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: when setting the power supply fluctuation to this standard or less, it is possible to suppress the slope detection. this is the standard when the power supp ly fluctuation is stable. *3: this time is to start the slope detection at next power on after power down and internal charge loss.
document number: 002- 0466 5 rev * a page 139 of 175 mb91580m/s series 11.4.4 multi - function serial csio timing (smr:md2 - 0="010"b) normal synchronous transfer (scr:spi=0) and serial clock output signa l detect level "h" (smr:scinv=0) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0. 0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0_0, sck0_1 * , sck1, sck2 * , sck3 * master mode c l =50pf 4 t cp p - ns sck ? sot delay time t slov i sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 +30 ns valid sin ? sck setup time t ivsh i sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 30 - ns sck ? valid si n hold time t shix i 0 - ns serial clock "h"pulse width t shsl sck0_0, sck0_1 * , sck1, sck2 * , sck3 * slave mode c l =50pf t cp p +10 - ns serial clock "l"pulse width t slsh 2 t cp p - 10 - ns sck ? sot delay time t slov e sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 ns valid sin ? sck setup time t ivsh e sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 10 - ns sck ? valid sin hold time t shix e 20 - ns sck fall time t f sck0_0, sck0_1 * , s ck1, sck2 * , sck3 * - 5 ns sck rise time t r sck0_0, sck0_1 * , sck1, sck2 * , sck3 * - 5 ns *: only available with mb91f583 a m/f584a m/f585am notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins durin g testing. ? the maximum baud rate is limited by the internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 140 of 175 mb91580m/s series t scyc v ol t slovi t ivshi t shixi v ih v il v oh v ol sck sot sin v ih v il v oh master mode t slsh v il t slove t ivshe t shixe v ih v il v oh v ol sck sot sin v ih v il t f v ih v il v ih t shsl t r v ih slave mode
document number: 002- 0466 5 rev * a page 141 of 175 mb91580m/s series normal synchronous transfer (scr:spi=0) and serial clock output signal detect le vel "l" (smr:scinv=1) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0 .0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0_0, sck0_1 * , sck1, sck2 * , sck3 * master mode c l =50p f 4 t cp p - ns sck ? sot delay time t sh ov i sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 +30 ns valid sin ? sck setup time t ivs li sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 30 - ns sck ? valid si n hold time t sl ix i 0 - ns serial clock "h"pulse width t shsl sck0_0, sck0_1 * , sck1, sck2 * , sck3 * slave mode c l =50pf t cp p +10 - ns serial clock "l"pulse width t slsh 2 t cp p - 10 - ns sck ? sot delay time t sh ov e sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 ns valid sin ? sck setup time t ivs le sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 10 - ns sck ? valid sin hold time t sl ix e 20 - ns sck fall time t f sck0_0, sck0_1 * , s ck1, sck2 * , sck3 * - 5 ns sck rise time t r sck0_0, sck0_1 * , sck1, sck2 * , sck3 * - 5 ns *: only available with mb91f583 a m/f584a m/f585am notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins durin g testing. ? the maximum baud rate is limited by the internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 142 of 175 mb91580m/s series t scyc v oh t shovi t ivsli t slixi v ih v il v oh v ol sck sot sin v ih v il v ol master mode t shsl v il t shove t ivsle t slixe v ih v il v oh v ol sck sot sin v ih v il t r v ih v il v ih t slsh t f v i l slave mode
document number: 002- 0466 5 rev * a page 143 of 175 mb91580m/s series spi compatible (scr:spi=1) and serial clock output signal detect level "h" (smr:s cinv=0) (t a : recommended operating conditions , v cc = 5.0v 10% , v ss =av ss =0 .0v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0_0, sck0_1 * , sck1, sck2 * , sck3 * master mode c l =50pf 4 t cp p - ns sck ? sot delay time t sh ov i sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 +30 ns valid sin ? sck setup time t ivs li sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 30 - ns sck ? valid sin hold time t sl ix i 0 - ns sot ? sck delay time t sovli sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * 2 t cp p - 30 - ns serial clock "h"pulse width t shsl sck0_0, sck0_1 * , sck1, sck2 * , sck3 * slave mode c l =50pf t cp p +10 - ns serial cl ock "l"pulse width t slsh 2 t cp p - 10 - ns sck ? sot delay time t sh ov e sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 ns valid sin ? sck setup time t ivs le sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin 2 * , sin3 * 10 - ns sck ? valid sin hold time t sl ix e 20 - ns sck fall time t f sck0_0, sck0_1 * , sck1, sck2 * , sck3 * - 5 ns sck rise time t r sck0_0, sck0_1 * , sck1, sck2 * , sck3 * - 5 ns *: only available with mb91f583 a m/f584a m/f585am notes: ? this i s the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 144 of 175 mb91580m/s series t scyc v ol t sovli t slixi v ih v il v oh v ol sck sot sin v ih v il v oh v oh v ol t ivsli t shovi v ol master mode t slsh v il t f t slixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivsle t shove v il v ih v ih v il t shsl t r * *: changes when writing to tdr register slave mode
document number: 002- 0466 5 rev * a page 145 of 175 mb91580m/s series spi compatible (scr:spi=1) and serial clock output signal detect level "l" (smr:scinv=1) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0.0 v) parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0_0, sck0_1 * , sck1, sck2 * , sck3 * master mode c l =50pf 4 t cp p - ns sck ? sot delay time t sl ov i sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * - 30 +30 ns valid sin ? sck setup time t ivs h i sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 30 - ns sck ? valid sin hold time t sh ix i 0 - ns sot ? sck delay time t s ovhi sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1, sot2 * , sot3 * 2 t cp p - 30 - ns serial clock "h" pulse width t shsl sck0_0, sck0_1 * , sck1, sck2 * , sck3 * slave mode c l =50pf t cp p +10 - ns serial clock "l" pulse width t slsh 2 t cp p - 10 - ns sck ? sot delay time t sl ov e sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sot0_0, sot0_1 * , sot1 , sot2 * , sot3 * - 30 ns valid sin ? sck setup time t ivs he sck0_0, sck0_1 * , sck1, sck2 * , sck3 * , sin0_0, sin0_1 * , sin1, sin2 * , sin3 * 10 - ns sck ? valid sin hold time t sh ix e 20 - ns sck fall time t f sck0_0, sck0_1 * , sck1, sck2 * , sck3 * - 5 ns sck rise time t r sck0_0, sck0_1 * , sck1, sck2 * , sck3 * - 5 ns *: only available with mb91f583 a m/f584a m/f585am notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximu m baud rate is limited by the internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 146 of 175 mb91580m/s series t scyc v oh t sovhi t shixi v ih v il v oh v ol sck sot sin v ih v il v ol v oh v ol t ivshi t slovi v oh master mode t shsl v il t r t shixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivshe t slove v il v ih v ih v il t slsh t f * *: changes when writing to tdr register slave mode
document number: 002- 0466 5 rev * a page 147 of 175 mb91580m/s series when the serial chip select is used (scscr:csen=1) ? serial clock output signal detect level "h" (smr :scin v=0) ? serial chip select inactive level "h" (scscr :cslvl=1) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0. 0v) parameter symbol pin name conditions value unit remarks min max scs ? sck setup time t cssi sck1, sck2 *4 , sck 3 *4 , scs1, scs2 *4 , scs3 *4 master mode c l =50pf t cssu *1 + 0 t cssu *1 + 50 ns sck ? scs hold time t cshi t cshd *2 -50 t cshd *2 +0 ns scs deselect time t csdi scs1, scs2 *4 , scs3 *4 -50+ 5 t c pp +t csds *3 +50+ 5 t c pp +t csds *3 ns scs ? sck setup time t csse sck1 , sck2 *4 , sck3 *4 , scs1, scs2 *4 , scs3 *4 slave mode c l =50pf 3t cp p +30 - ns sck ? scs hold time t cshe 0 - ns scs deselect time t csde scs1, scs2 *4 , scs3 *4 3t cp p +30 - ns scs ? sot delay time t dse scs1, scs2 *4 , scs3 *4 , sot1, sot2 *4 , sot3 *4 - 40 ns scs ? sot delay time t dee 0 - ns *1: t cs su =s cstr:css u7 -0 s erial chip select timing operation clock *2: t cs hd =s cstr:cshd7 -0 s erial chip select timing operation clock *3: t cs ds =sc str:csds15 -0 s erial chip select timing operation clock *4: only available with mb91f583 a m/f584a m/f585am for details of *1, *2 and *3 above, see hardware manual. notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 148 of 175 mb91580m/s series sck output sot (normal sync transfer) sot (spi compatible) t cssi scs output t cshi t csdi master mode sck input sot (normal sync transfer) sot (spi compatible) t csse scs input t cshe t csde t dse t dee slave mode
document number: 002- 0466 5 rev * a page 149 of 175 mb91580m/s series when the serial chip select is used (scscr:csen=1) ? serial clock output signal detect level "l" (smr:scinv=1) ? serial chip select inactive level "h" (scscr:cslvl=1) (t a : recommended operating conditions , v cc = 5.0v 10 %, vss=avss=0.0v) parameter symbol pin name conditions value unit remarks min max scs ? sck setup time t cssi sck1, sck2 *4 , sck3 *4 , scs1, s cs2 *4 , scs3 *4 master mode c l =50pf t cssu *1 + 0 t cssu *1 + 50 ns sck ? scs hold time t cshi t cshd *2 -50 t cshd *2 +0 ns scs deselect time t csdi scs1, scs2 *4 , scs3 *4 -50+ 5 t c pp +t csds *3 +50+ 5 t c pp +t csds *3 ns scs ? sck setup time t csse sck1, sck2 *4 , sc k3 *4 , scs1, scs2 *4 , scs3 *4 slave mode c l =50pf 3t cp p +30 - ns sck ? scs hold time t cshe 0 - ns scs deselect time t csde scs1, scs2 *4 , scs3 *4 3t cp p +30 - ns scs ? sot delay time t dse scs1, scs2 *4 , scs3 *4 , sot1, sot2 *4 , sot3 *4 - 40 ns scs ? sot delay time t dee 0 - ns *1: t cs su =s cstr:css u7 -0 s erial chip select timing operation clock *2: t cs hd =s cstr:cshd7 -0 s erial chip select timing operation clock *3: t cs ds =sc str:csds15 -0 s erial chip select timing operation clock *4: only availab le with mb91f583 a m/f584a m/f585am for details of *1, *2 and *3 above, see hardware manual. notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by th e internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 150 of 175 mb91580m/s series sck output sot (normal sync transfer) sot (spi compatible) t cssi scs output t cshi t csdi master mode sck input sot (normal sync transfer) sot (spi compatible) t csse scs input t cshe t csde t dse t dee slave mode
document number: 002- 0466 5 rev * a page 151 of 175 mb91580m/s series when the serial chip select is used (scscr:csen=1) ? serial clock output signal detect level "h" (smr :scinv=0) ? serial chip select inactive level "l" (scscr:c slvl=0) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0.0 v) parameter symbol pin name conditions value unit remarks min max scs ? sck setup time t cssi sck1, sck2 *4 , sck3 *4 , scs1, scs2 *4 , sc s3 *4 master mode c l =50pf t cssu *1 + 0 t cssu *1 + 50 ns sck ? scs hold time t cshi t cshd *2 -50 t cshd *2 +0 ns scs deselect time t csdi scs1, scs2 *4 , scs3 *4 -50+ 5 t c pp +t csds *3 +50+ 5 t c pp +t csds *3 ns scs ? sck setup time t csse sck1, sck2 *4 , sck3 *4 , scs 1, scs2 *4 , scs3 *4 slave mode c l =50pf 3t cp p +30 - ns sck ? scs hold time t cshe 0 - ns scs deselect time t csde scs1, scs2 *4 , scs3 *4 3t cp p +30 - ns scs ? sot delay time t dse scs1, scs2 *4 , scs3 *4 , sot1, sot2 *4 , sot3 *4 - 40 ns scs ? sot del ay time t dee 0 - ns *1: t cs su =s cstr:css u7 -0 s erial chip select timing operation clock *2: t cs hd =s cstr:cshd7 -0 s erial chip select timing operation clock *3: t cs ds =sc str:csds15 -0 s erial chip select timing operation clock *4: only available with mb 91f583 a m/f584a m/f585am for details of *1, *2 and *3 above, see hardware manual. notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operation clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 152 of 175 mb91580m/s series sck output sot (normal sync transfer) sot (spi compatible) t cssi scs output t cshi t csdi master mode sck input sot (normal sync transfer) sot (spi compatible) t csse scs input t cshe t csde t dse t dee slave mode
document number: 002- 0466 5 rev * a page 153 of 175 mb91580m/s series when the serial chip select is used (scscr:csen=1) ? serial clock output signal detect level "l" (smr:scinv=1) ? serial chip select inactive level "l" (scscr:cslvl=0) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0. 0v) parameter symbol pin name conditions value unit remarks min max scs ? sck setup time t cssi sck1, sck2 *4 , sck3 *4 , scs1, scs2 *4 , scs3 *4 mas ter mode c l =50pf t cssu *1 + 0 t cssu *1 + 50 ns sck ? scs hold time t cshi t cshd *2 -50 t cshd *2 +0 ns scs deselect time t csdi scs1, scs2 *4 , scs3 *4 -50+ 5 t c pp +t csds *3 +50+ 5 t c pp +t csds *3 ns scs ? sck setup time t csse sck1, sck2 *4 , sck3 *4 , scs1, scs2 * 4 , scs3 *4 slave mode c l =50pf 3t cp p +30 - ns sck ? scs hold time t cshe 0 - ns scs deselect time t csde scs1, scs2 *4 , scs3 *4 3t cp p +30 - ns scs ? sot delay time t dse scs1, scs2 *4 , scs3 *4 , sot1, sot2 *4 , sot3 *4 - 40 ns scs ? sot delay time t dee 0 - ns *1: t cs su =s cstr:css u7 -0 s erial chip select timing operation clock *2: t cs hd =s cstr:cshd7 -0 s erial chip select timing operation clock *3: t cs ds =sc str:csds15 -0 s erial chip select timing operation clock *4: only available with mb91f583 am /f584 a m/f585am for details of *1, *2 and *3 above, see hardware manual. notes: ? this is the ac characteristic in clk synchronized mode. ? c l is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operati on clock used and other parameters. see hardware manual for details.
document number: 002- 0466 5 rev * a page 154 of 175 mb91580m/s series sck output sot (normal sync transfer) sot (spi compatible) t cssi scs output t cshi t csdi master mode sck input sot (normal sync transfer) sot (spi compatible) t csse scs input t cshe t csde t dse t dee slave mode
document number: 002- 0466 5 rev * a page 155 of 175 mb91580m/s series uart (async serial interface) timing (smr:md2 - 0="000"b, "001"b) when the external clock is selected (bgr:ext=1) (t a : recommended operati ng conditions , v cc = 5.0v 10%, v ss =av ss =0 .0v) parameter symbol pin name conditions value unit remarks min max serial clock "l" pulse width t slsh sck0_0, sck0_1 * , sck1, sck2 * , sck3 * c l =50pf t cp p +10 - ns serial clock "h" pulse width t shsl t cp p +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns *: only available with mb91f583 a m/f584a m/f585am sck t shsl v il v ih v ih t r t slsh t f v il v ih v il when the external clock is selected lin interface (v2.1)( lin communication control interface (v2.1)) timing (smr:md2 - 0="011"b) when the ex ternal clock is selected (bgr:ext=1) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss =0 .0v) parameter symbol pin name conditions value unit remarks min max serial clock "l" pulse width t slsh sck0_0, sck0_1 * , sck1, sck2 * , sck3 * c l =50pf t cp p +10 - ns serial clock "h" pulse width t shsl t cp p +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns *: only available with mb91f583 a m/f584a m/f585am sck t shsl v il v ih v ih t r t slsh t f v il v ih v il when the external clock is selected
document number: 002- 0466 5 rev * a page 156 of 175 mb91580m/s series i 2 c timing (smr:md2 - 0="100"b) (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss = 0.0v) parameter symbol pin name conditions standard mode high - speed mode *3 unit remarks min max min max scl clock frequency f scl sck0_0 , sck0_1 *5 , sck2 *5 , sck3 *5 (scl) c l =50pf r= (v p / i ol ) *1 0 100 0 400 khz "repeat start condition" hold time sd a s cl t hdsta sck0_0 , sck0_1 *5 , sck2 *5 , sck3 *5 (scl) sot0_0, sot0_1 *5 , sot2 *5 , sot3 *5 (sda) 4.0 - 0.6 - s "l" width for scl clock t low sck0_0 , sck0_1 *5 , sck2 *5 , sck3 *5 (scl) 4.7 - 1.3 - s "h" width for scl clock t high 4.0 - 0.6 - s "r epeat start condition" setup time scl sda t susta sck0_0 , sck0_1 *5 , sck2 *5 , sck3 *5 (scl) sot0_0, sot0_1 *5 , sot2 *5 , sot3 *5 (sda) 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45 *2 0 0.9 0 *3 s data setup time sda scl t su dat 250 - 100 - n s "stop condition" setup time scl sda t susto 4.0 - 0.6 - s bus free time between "stop condition" and "start condition" t buf - 4.7 - 1.3 - s noise filter t sp - 2 t cpp *4 - 2 t cpp *4 - ns *1: r and c l represent the pull - up resistance and load capacitance of the scl and sda output lines, respectively. v p shows that the power supply voltage of the pull - up resistor and i ol shows the v ol guarantee current. *2: the maximum t hddat only has to be met if the device does not exten d the "l" width (t low ) of the scl signal. *3: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4: t cpp is the peripheral clock cycle time. adjust the clock of the peripheral bus to 8mhz or more when using i 2 c. *5: only available with mb91f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 157 of 175 mb91580m/s series sda scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto 11.4.5 timer input timing (t a : recommended operating conditions , v cc = 5.0v 10%, v ss =av ss = 0.0v) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tin0 to tin 3 , in0 to in3, frck0 to frck5, tioa 1, tiob 0, tiob 1 - 4t cp p - ns ain0,ain1, bin0,bin1, zin0,zin1 - 2t cp p - ns ? time r input timing v ih v il tinx inx frckx tioax,tiobx ainx,binx,zinx t tiwl t tiwh v ih v il 11.4.6 trigger input timing (t a : recommended operating conditions , v cc = 5.0v 10% v ss =av ss =0 .0v) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl int0 to int 6, int7 * , adtg 0 to adtg 2, r x0 , rx 1 * , trg0 , trg 1 , dtti0 - 5t cp p - ns 1 - s at stop mode *: only available with mb91f583 a m/f584a m/f585am
document number: 002- 0466 5 rev * a page 158 of 175 mb91580m/s series ? trigger input timing v ih v il t trgl t trgh v ih v il intx adtgx rxx trgx dttix 11.4.7 nmi input timing (t a : recommended operating conditions , v cc =5.0v 10%, v ss =av ss =0 .0v) parameter symbol pi n name conditions value unit remarks min max input pulse width t nmil nmix - 4 t c pp - ns ? nmix input timing v ih nmix t nmil v ih v il v il
document number: 002- 0466 5 rev * a page 159 of 175 mb91580m/s series 11.4.8 low - voltage detection (external low - voltage detection) (t a : recommended operating conditions , v ss =av ss =0 .0v) parameter symbol pin name conditions value unit remarks min typ max power supply voltage range v dp5 vcc5 - 3.7 - 5.5 v detection voltage v d l vcc5 * 1 - 8% 3.9 +8% v when power supply voltage falls and detection level is set initially hysteresis width v hys vcc5 - - 0.1 - v when power supply voltage rises low - voltage detection time td - - - - 3 0 s power supply voltage fluctuation rate - vcc5 - - 2 - 2 v/ms *2 *1: if the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low - voltage detection time (td), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: in order to perform the low - voltage detection at the detection voltage (v dl ), be sure to suppress fluctuation of the power supply within the limits of the power supply voltage fluctuation rate. 11.4.9 low - voltage detection (internal low - voltage detection) (t a : recommended operating conditions , v ss =av ss = 0.0v) parameter symbol pin name conditions value unit remarks min typ max power supply voltage range v rdp5 - - 1.1 - 1.3 v detection voltage v rdl - * 0.8 0.9 1.0 v when power supply voltage falls hysteresis width v rhys - - - 0.1 - v when power supply voltage rises low - voltage detection time - - - - - 30 s *: if the fluctuation of the power supply is faster than the low - voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range.
document number: 002- 0466 5 rev * a page 160 of 175 mb91580m/s series 11.5 a/d converter 11.5.1 electrical characteristic s (t a : recommended operating conditions , v cc = 5.0v 10%, av cc =5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit non linearity error - - - 4.0 - +4.0 lsb differential linearity error - - - 1 .9 - + 1.9 lsb zero transition voltage v ot an0 to an14, an16 to an18 *3 , an19, an20, an21 to an23 *3 avrl+ 0.5lsb - 20 - avrl+ 0.5lsb+20 m v 1lsb= (vfst - vot)/40 94 full - scale transition voltage v fst an0 to an14, an16 to an18 *3 , an19, an20, an21 to an23 *3 avrh - 1.5lsb - 20 - avrh - 1.5lsb+20 m v sampling time t smp - 0.3 - 12 s *1 compare time t cmp - 0.7 - 28 s * 1 a/d conversion time t cnv - 1.0 - 40 s * 1 analog port input current i ain an0 to an14, an16 to an18 *3 , an19, an20, an21 to an23 *3 - 1.0 - 1.0 a v avss v ain v avcc analog input voltage v ain an0 to an14, an16 to an18 *3 , an19, an20, an21 to an23 *3 av ss - avr h v reference voltage avr h avrh0, avrh1 4 . 5 - 5.5 v a v cc avrh avr l avrl0, avrl1, - 0.0 - v power supply current i a avcc0, avcc1 - 1.5 2.1 ma 3 units operating i ah - - 25 a 3 units operating * 2 i r avrh0, avrh1 - 3 6 m a 3 units operating i rh - - 4.8 a 3 units operating * 2 variation between channels - an0 to an14, an16 to an18 *3 , an19, an20, an21 to an23 *3 - - 4 lsb every 1 unit * 4 *1: ti me for each channel. *2: the power supply current (vcc=avcc=5.0v) is specified if the a/d converter is not operating and cpu is stopped. *3: only available with mb91f583 a m/f584a m/f585am * 4 : unit0 an0 to an7 unit1 an8 to an14 unit2 an16 to an23
document number: 002- 0466 5 rev * a page 161 of 175 mb91580m/s series 11.5.2 definiti on of terms resolution: analog variation that is recognized by an a/d converter. linearity error : deviation of the actual conversion characteristics from a straight line that connects the zero transition point ("0000 0000 00 00" "000 0 0000 0001") to the full - scale transition point ("1111 1111 1110" "1111 1111 1111"). differential linearity error: deviation of the input voltage from the ideal value that is required to change the output code by 1lsb. linearity error di f ferential linearity error linearity error of digital output n = v nt - {1lsb(n-1) + v ot } [lsb] 1lsb differential linearity error of digital output n = v (n + 1)t - v nt -1 lsb [lsb] 1lsb 1lsb = v fst - v ot [v] 4094 v ot : voltage at which the digital output changes from "000 h " to "001 h ". v fst : voltage at which the digital output changes from "ffe h " to "fff h ". a vss (a vrl) a vrh a vrh actual conversion characteristics {1 lsb (n - 1) + v ot } a vss (a vrl) v fs t v nt v ot (actually-measured value) v (n+1) t v nt ideal characteristics actual conversion characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output (actually-measured value) (actually- measured value) (actually-measured value) analog input analog input (actually-measured value) digital output n - 1 n - 2 n n + 1 fff ffe ffd 004 003 002 001 11.5.3 notes on using a/d converter when the external impedance is too high, the sampling time for analog voltages may not be sufficient. in this case, it is recommended to connect the capacitor (approx. 0.1 f) to the analog input pin.
document number: 002- 0466 5 rev * a page 162 of 175 mb91580m/s series ? ana log input circuit model r c 12bit a/d 1.9k (max) 8.3pf (max) (4.5v avcc 5.5v) note: listed values must be considered as reference values. r c sampling on comparator analog input
document number: 002- 0466 5 rev * a page 163 of 175 mb91580m/s series 11.6 d/a converter (t a : recommended operating conditions , v cc = av cc =5.0v 10%, v ss =av ss =0.0v) parameter symbol pin name value unit remarks min typ max resolution - - - - 10 bit differential linearity error - - - 4.0 - +4.0 ls b when the analog output voltage is 0.5v to 4.5v 11.7 flash memory 11.7.1 electrical characteristics parameter value unit remarks min typ max sector erase time - 200 800 ms 8 kbyte sector *1 excluding internal preprogramming time - 300 1100 ms 8 kbyte sector *1 in cluding internal preprogramming time - 400 2000 m s 64 kbyte sector *1 excluding internal preprogramming time - 700 3700 m s 64 kbyte sector *1 in cluding internal preprogramming time 8 - bit writing time - 9 288 s excluding overhead time at system lev el *1 16- bit writing time - 12 384 s excluding overhead time at system level *1 ecc writing time - 9 288 s excluding overhead time at system level *1 erase cycle *2 / data ret ention time 1,000 cycles/20 years, 10,000 cycles/10 years, 100,000 cycles/5 years - - - average temperature t a =+85 c *3 *1: the guaranteed value for erase up to 100,000 cycles *2: number of erase cycles for each sector *3: this value comes from the technology qualification (using arrhenius equation to translate high temperature measur ements into normalized value at + 85c).
document number: 002- 0466 5 rev * a page 164 of 175 mb91580m/s series 11.7.2 notes while the flash memory is written or erased , shutdown of the external power (vcc) is prohibited. in the application system where vcc might disappear while writing or erasing , be sure to turn the power off by using an external low - voltage detect ion function . to put it concretely, after the external power supply voltage falls below the detection voltage (v dl * ), hold vcc at 2.7v or more within the duration calculated by the following expression: td * [ s] + (pclk c ycle [ s] 257) + 50[ s] *: see "4. ac characteristics (8) low - voltage detection (external low - voltage detection)."
document number: 002- 0466 5 rev * a page 165 of 175 mb91580m/s series 12. example characteristics this characteristic is an actual value of the arbitrary sample. it is not the guaranteed value. 10.00 100.00 -50 0 50 100 150 i cc 5 [ma] t a [oc] normal operation (1)fcp=128mhz, fcpp=32mhz, fcpm=128mhz, flexray=on (2)fcp=128mhz, fcpp=40mhz, fcpm=40mhz, flexray=on (3)f cp=80mhz, fcpp=40mhz, fcpm=80mhz, flexray=on (v cc = 5.5v) (1) (2) (3) (4) (4)f cp=80mhz, fcpp=40mhz, fcpm=40mhz, flexray=on 10.00 100.00 -50 0 50 100 150 i cc 5 [ma] t a [oc] normal operation (v cc = 5.5v) (1) (2) (3) (4) (1)fcp=128mhz, fcpp=32mhz, fcpm=128mhz, flexray=off (2)fcp=128mhz, fcpp=40mhz, fcpm=40mhz, flexray=off (3)f cp=80mhz, fcpp=40mhz, fcpm=80mhz, flexray=off (4)f cp=80mhz, fcpp=40mhz, fcpm=40mhz, flexray=off
document number: 002- 0466 5 rev * a page 166 of 175 mb91580m/s series 10.000 100.000 -50 0 50 100 150 i cc s5/ i cc bs5 [ma] t a [oc] sleep mode cpu sleep(128mhz) bus sleep (128mhz) (v cc = 5.5v)
document number: 002- 0466 5 rev * a page 167 of 175 mb91580m/s series 0.001 0.010 0.100 1.000 10.000 -50 0 50 100 150 i cc t5 [ma] t a [oc] watch mode main osc (4mhz) external clock (4mhz) (v cc = 5.5v) (v cc = 5.5v) 0.001 0.010 0.100 1.000 10.000 -50 0 50 100 150 i cc h5 [ma] t a [oc] stop mode (v cc = 5.5v)
document number: 002- 0466 5 rev * a page 168 of 175 mb91580m/s series 0.01 0.10 1.00 10.00 100.00 1000.00 -50 0 50 100 150 i cc t52 [ a ] t a [oc] watch mode(power off) main osc (4mhz) external clock (4mhz) (v cc = 5.5v) (v cc = 5.5v) 0.01 0.10 1.00 10.00 100.00 1000.00 -50 0 50 100 150 i cc h52 [ a ] t a [oc] stop mode(power off) (v cc = 5.5v)
document number: 002- 0466 5 rev * a page 169 of 175 mb91580m/s series 13. ordering information part number package* mb91f583 a mgpmc - gte1 mb91f584 a mgpmc - gte1 mb91f585 a mgpmc - gte1 mb91f583 a mhpmc - gte1 mb91f584 a mhpmc - gte1 mb91f585 a mhpmc - gte1 mb91f583 a mjpmc - gte1 mb91f584 a mjpmc - gte1 mb91f585 a mjpmc - gte1 mb91f583 a mkpmc - gte 1 mb91f584 a mkpmc - gte1 mb91f585 a mkpmc - gte1 100- pin plastic lqfp ( fpt - 100p - m20 ) mb91f583 a sgpmc1 - gte1 mb91f584 a sgpmc1 - gte1 mb91f585 a sgpmc1 - gte1 mb91f583 a shpmc1 - gte1 mb91f584 a shpmc1 - gte1 mb91f585 a shpmc1 - gte1 mb91f583 a sjpmc1 - gte1 mb91f584 a sjpmc1 - gte1 mb91f585 a sjpmc1 - gte1 mb91f583 a skpmc1 - gte1 mb91f584 a skpmc1 - gte1 mb91f585 a skpmc1 - gte1 64- pin plastic lqfp ( fpt - 64p - m24 ) *: for details of the package , see package dimensions
document number: 002- 0466 5 rev * a page 170 of 175 mb91580m/s series 14. package dimensions 100-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 14.0 mm 14.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.65 g code (reference ) p-lfqfp100-14 14-0.5 0 100-pin plastic lqfp (fpt -100p-m20) (fpt-100p-m20) c 2005 -2010 fujitsu semiconductor limited f100031s-c-3-5 16.00 0.20(.630 .008)sq 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.008 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" index .059 ? .004 +.008 ? 0.10 +0.20 1.50 (mounting height) 0 ~8 0.50 0.20 (.020 .008 ) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) details of "a" part (stand off) * 14.00 0.10(.551 .004)sq dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002- 0466 5 rev * a page 171 of 175 mb91580m/s series 64-pin plastic lqfp lead pitch 0.50 m m package width package length 10.0 10.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.32 g code (reference ) p-lfqfp64-1 0 10-0.50 64-pin plastic lqf p (fpt-64p-m24) (fpt -64p-m24) lead no. details of "a" part 0.25(.010) (stand off) 0.100.10 0.600.15 (.024.006) 0.500.20 (.020.008) 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ~8 "a" 0.08(.003) 0.1450.055 (.006.002) 0.08(.003) m (.008.002) 0.200.05 0.50(.020) 12.000.20(.472.008)sq index 49 64 33 48 17 32 16 1 2005-2010 fujitsu semiconductor limited f64036s-c-1-3 c (mounting height) *10.000.10(.394.004)sq dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. (.004.004)
document number: 002- 0466 5 rev * a page 172 of 175 mb91580m/s series 15. major changes spansion publication nu mber: mb91f585amg_ds705 - 00013 page section change results revision 1.0 - - initial release revision 2.0 - - the product series name should be corrected. mb91f585mg mb91f585amg mb91f585mh mb91f585amh mb91f585mj mb91f585a mj mb91f585mk mb91f585amk mb91f584mg mb91f584amg mb91f584mh mb91f584amh mb91f584mj mb91f584amj mb91f584mk mb91f584amk mb91f583mg mb91f583amg mb91f583mh mb91f583amh mb91f583mj mb91f583amj mb91f583mk mb91f583amk mb91f585sg mb91f585asg mb91f585sh mb91f585ash mb91f585sj mb91f585asj mb91f585sk mb91f585ask mb91f584sg mb91f584asg mb91f584sh mb91f584ash mb91f584sj mb91f584asj mb91f584sk mb91f584ask mb91f583sg mb91f583asg mb91f583sh mb91f583ash mb91f583sj mb91f583asj mb91f583sk mb91f583ask 2 features the features of cr oscillation should be corrected. oscillation frequency: 100khz, with frequency accuracy 10% oscillation frequency: 100khz, with frequency accuracy 50% (pre - trimming) 22 i/o circuit type the specification of "h" level input voltage and "l" level input voltage of flexray should be corrected. flexray input (0. 65 vcc/0.3 5 vcc) flexray input (0 . 7 vcc/0.3vcc)
document number: 002- 0466 5 rev * a page 173 of 175 mb91580m/s series page section change results 33 memory map the memory map should be corrected. the address of "reset vector table" and "interrupt vector table" should be added 54, 85 i/o map address:00150c h the register name should be corrected . stmcr00 stmcr0 54,55,85 i/o map addr ess: 00150 e h , 001510 h , 001511 h , 001512 h , 001513 h the registers should be deleted. scs cr0,scstr30,scstr20,scstr10,scstr00 63 ,92 i/o map address:00d310 h the initial values of mhds should be corrected. - 0000000 - 0000000 - 0000000 10000000 - 0 000000 - 0000000 - 0000000 00000000 104 electrical characteristics dc caharacteristics the specification of "h" level input voltage of p021 - p023,p025 - p027 should be corrected. min:0.65 vcc min: 0.7 vcc 105 electrical characteristics dc caharacteristi cs the specification of " l " level input voltage of p021 - p023,p025 - p027 should be corrected. m ax : 0. 35 vcc m ax : 0. 3 vcc 111 electrical characteristics ac characteristics main clock timing t he remarks of "can pll jitter" should be deleted. 111 elec trical characteristics ac characteristics main clock timing the specifications of " the built - in cr oscillation frequency " should be corrected. min: 90khz, m ax : 110khz min:50khz max:150khz, - - company name and layout design change note: please see ?do cument history? about later revised information.
document number: 002- 0466 5 rev * a page 174 of 175 mb91580m/s series document history document title: mb91f583 amg/amh/amj/amk/asg/ash/asj/ask , mb91f584amg/amh/amj/amk/asg/ash/asj/ask , mb91f585amg/amh/amj/amk/asg/ash/asj/ask, mb91580m/s series fr81s, 32 - bit microcontroller datasheet document number: 002- 04665 revision ecn orig. of change submission date description of change ** ? kojm 04/18 /201 4 migrated to cypress and assig ned document number 002 - 04665. no change to document contents or format. * a 5139690 kojm 03/2 9 /2016 updated to cypress template
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